FPGA Implementation of Multi-scale Face Detection Using HOG Features and SVM Classifier

• Autorzy: Drożdż M. , Kryjak T.

Identyfikatory

DOI

10.1515/ipc-2016-0014

• Języki publikacji: EN

Abstrakty

EN

In this paper an FPGA based embedded vision system for face detection is presented. The sliding detection window, HOG+SVM algorithm and multi-scale image processing were used and extensively described. The applied computation parallelizations allowed to obtain real-time processing of a 1280 × 720 @ 50Hz video stream. The presented module has been verified on the Zybo development board with Zynq SoC device from Xilinx. It can be used in a vast number of vision systems, including diver fatigue monitoring.

Słowa kluczowe

EN

face detection; HOG; SVM; FPGA

• Wydawca: Instytut Telekomunikacji i Informatyki Uniwersytetu Technologiczno-Przyrodniczego w Bydgoszczy
• Czasopismo: Image Processing & Communications
• Rocznik: 2016
• Tom: Vol. 21, no. 3
• Strony: 27--44
• Opis fizyczny: Bibliogr. 25 poz., rys., tab.

Twórcy

autor

Drożdż M.

• AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Kraków

autor

Kryjak T.

• AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Kraków

Bibliografia

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Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).