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Single charge manipulation for useful electronic functionalities has become an exciting and fast-paced direction of research in recent years. In structures with dimensions below about 100 nm, the physics governing the device operation turn out to be strikingly different than in the case of larger devices. The presence of even a single charge may completely suppress current flow due to the basic electronelectron repulsion (so called Coulomb blockade effect) [1]. It is even more exciting to control this effect at the level of single-electron/single-atom interaction. The atomic entity can be one donor present in silicon lattice with a Coulombic potential well. In principle, it can accommodate basically a single electron. We study the electrical behavior of nanoscale-channel silicon-on-insulator field-effect transistors (SOI-FETs) that contain a discrete arrangement of donors. The donors can be utilized as "stepping stones" for the transfer of single charges. This ability opens the doors to a rich world of applications based on the simple interplay of single charges and single atoms, while still utilizing mostly conventional and well established fabrication techniques. In this work, we distinguish the effects of single-electron transport mediated by one or few dopants only. Furthermore, we show how the single-electron/single-donor interaction can be tuned by using the external biases. We demonstrate then by simulation and experiment the feasibility of single-electron/bit transfer operation (single-electron turnstile).
Content available remote 3D quantum mechanical simulation of square nanowire MOSFETs by using NEGF method
In order to investigate the specifications of nanoscale transistors, we have used a three dimensional (3D) quantum mechanical approach to simulate square cross section silicon nanowire (SNW) MOSFETs. A three dimensional simulation of silicon nanowire MOSFET based on self consistent solution of Poisson-Schrödinger equations is implemented. The quantum mechanical transport model of this work uses the non-equilibrium Green’s function (NEGF) formalism. First, we simulate a double-gate (DG) silicon nanowire MOSFET and compare the results with those obtained from nanoMOS simulation. We understand that when the transverse dimension of a DG nanowire is reduced to a few nanometers, quantum confinement in that direction becomes important and 3D Schrödinger equation must be solved. Second, we simulate gate-all-around (GAA) silicon nanowire MOSFETs with different shapes of gate. We have investigated GAA-SNW-MOSFET with an octagonal gate around the wire and found out it is more suitable than a conventional GAA MOSFET for its more I on/I off, less Drain-Induced-Barrier-Lowering (DIBL) and less subthreshold slope.
In this study a two-step short wet etching was implemented for the black silicon formation. The proposed structure consists of two steps. The first step: wet acidic etched pits-like morphology with a quite new solution of lowering the texturization temperature and second step: wires structure obtained by a metal assisted etching (MAE). The temperature of the process was chosen due to surface development control and surface defects limitation during texturing process. This allowed to maintain better minority carrier lifetime compared to etching in ambient temperature. On the top of the acidic texture the wires were formed with optimized height of 350 nm. The effective reflectance of presented black silicon structure in the wavelength range of 300-1100 nm was equal to 3.65%.
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