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2 Poznan University of Technology Academic Journals. Electrical Engineering

2 2012

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FPGA implementation of reverse residue conversion based on the new Chinese Remainder Theorem II- Part II: experimental results

100%

Ulman Z. , Czyżak M. , Smyk R.

tom No. 71

139--147

This work describes a hardware realization of the converter of numbers from the Residue Number System (RNS) to the binary system. The converter is based on the new form of the Chinese Remainder Theorem (CRT) termed the New CRT II. The theoretical aspects of conversion by this method have been described in Part I. The implementation of the converter has been carried out in the Xilinx FPGA environment. The general architecture of the system is shown, also the realizations of the selected blocks of the converter are described. The hardware amount and attainable pipelining rate are given. The converter has been realized for the RNS base composed of eight 5-bit moduli that gives the dynamic range of about 37 bits.

FPGA implementation of reverse residue conversion based on the new Chinese Remainder Theorem II- Part I

100%

Ulman Z. , Czyżak M. , Smyk R.

tom No. 71

133--138

This work describes a derivation and an implementation of the algorithm of conversion from the Residue Number System (RNS) to the binary system based on the new form of the Chinese Remainder Theorem (CRT) termed the New CRT II. The new form of the CRT does not require the modulo M operation, where M is the residue number system range, but a certain number of multipliers is needed. Because in the FPGA environments the multipliers or the special DSP blocks are available, so they can be used in the converter realization. The main aim of the work is to examine experimentally the needed hardware amount and the influence of the multipliers on the maximum pipelining frequency. In Part I the derivation of the conversion algorithm is described. In Part II the hardware implementation of the converter in the FPGA technology is shown.