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2014 | R. 90, nr 1 | 111--114
Tytuł artykułu

Dynamic Ruleset Based Online Concurrent Testing of Functional Faults for Embedded Controllers

Wybrane pełne teksty z tego czasopisma
Warianty tytułu
PL
Online współbieżne testowanie błędów w kontrolerach wbudowanych
Języki publikacji
EN
Abstrakty
EN
Concurrent fault testing is mandatory in critical embedded systems like automobile applications. Architectures of concurrent testing are proposed in the present work, where testing is non-intrusive. The concept that embedded program has several tasks is exploited here. The hardware overhead of the test architecture implemented on the controller of OC8051 is minimal. It is easily scalable. Error detection latency is kept at a few cycles and cumulative functional error coverage is 100%. The architectures are compared with the best of the existing methods.
PL
Współbieżne testowanie jest często obowiązkowe w systemach wbudowanych. W artykule zaprezentowano architektury tego typu systemów gdzie wbudowany program wykonuje wiele zadań. Analizowano opóźnienie w wykrywaniu błędów oraz uwarunkowania sprzętowe.
Wydawca

Rocznik
Strony
111--114
Opis fizyczny
Bibliogr. 26 poz., rys., tab.
Twórcy
autor
autor
Bibliografia
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  • 4. K. Mohanram, and N. A. Touba, "Cost-Effective Approach for Reducing Soft Error Rate in Logic Circuits", in Proc. of the International Test Conference, 2003, pp. 893–901.
  • 5. G. Aksenova, and E. Sogomonyan, "Design of Self-Checking Built-in Check Circuits for Automata with Memory", Automation and Remote Control, vol. 36, no. 7, pp. 1169–1177, 1975.
  • 6. S. Dhawan, and R. C. D. Vries, "Design of Self-Checking Sequential Machines", IEEE Transactions on Computers, vol. 37, no. 10, 1988, pp. 1280–1284.
  • 7. C. Zeng, N. Saxena, and E.J. McCluskey, "Finite State Machine Synthesis with Concurrent Error Detection", in Proc. of the International Test Conference, 1998, pp. 672–679.
  • 8. D. Das, and N. A. Touba, "Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes", Journal of Electronic Testing: Theory and Applications, vol. 15, no. 2, 1999, pp. 145–155.
  • 9. N. K. Jha and S.-J. Wang, "Design and Synthesis of Self- Checking VLSI Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 6, 1993, pp. 878–887.
  • 10. R. A. Parekhji, G. Venkatesh, and S. D. Sherlekar, "Concurrent Error Detection Using Monitoring Machines", IEEE Design and Test of Computers, vol. 12, no. 3, 1995, pp. 24–32.
  • 11. S. Almukhaizim, P. Drineas, and Y. Makris, "Entropy-Driven Parity-Tree Selection for Low-Overhead Concurrent Error Detection in Finite State Machines", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 8, 2006, pp. 1547-1554.
  • 12. Costas-Perez, L.; Rodriguez-Andina, J.J., "Algorithmic Concurrent Error Detection in Complex Digital-ProcessingSystems", Design & Test of Computers, IEEE, vol. 26, no. 1, pp. 60,67, Jan.-Feb. 2009
  • 13. Mandjavidze, I.; Romanteau, T., "Embedding online test and monitoring features in real time hardware systems", Real Time Conference (RT), 2010 17th IEEE-NPSS, vol., no., pp. 1,8, 24-28 May 2010
  • 14. Abdelfattah, M.S.; Bauer, L.; Braun, C.; Imhof, M.E.; Kochte, M.A.; Hongyan Zhang; Henkel, J.; Wunderlich, H., "Transparent structural online test for reconfigurable systems", On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International, vol., no., pp. 37,42, 27-29 June 2012
  • 15. M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, and Y. Makris, "Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller", IEEE Trans. Computers, vol. 60, no. 9, pp. 1260-1273, 2011.
  • 16. I. Voyiatzis, A. Paschalis, D. Gizopoulos, C. Halatsis, F.S. Makri, and M. Hatzimihail, "An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set", IEEE Trans. on Computers, vol. 57, no. 8, pp. 1012-1022, Aug. 2008
  • 17. J. Shen and J. Abraham, "Native mode functional test generation for processors with applications to self test and design validation", in Proc. IEEE Int. Test Conf., Oct. 1998, pp. 990–999.
  • 18. Sandeep Sharma, Ashutosh Gupta, ManojDuhan and Solomon Raju Kota, "Design of Partially Reconfigurable Computing System and Implementation on Virtex-4 FPGA", The IUP Journal of Science & Technology, Vol. 6, Sept., 2010
  • 19. P. Philemon Daniel and RajeevanChandel, "A Flexible Programmable. Memory BIST Architecture", IETE Journal of Education, vol. 51, pp. 67-74, Dec 2010.
  • 20. Johnson, B.W.; Aylor, J.H.; Hana, H.H., "Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder", Solid-State Circuits, IEEE Journal of, vol. 23, no. 1, pp. 208,215, Feb. 1988
  • 21. Rajabzadeh, A.; Mohandespour, M.; Miremadi, G., "Error detection enhancement in COTS superscalar processors with event monitoring features", Dependable Computing, 2004. Proceedings. 10th IEEE Pacific Rim International Symposium on, vol., no., pp. 49-54, 3-5 March 2004
  • 22. Khan, O.; Kundu, S., "Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors", Dependable and Secure Computing, IEEE Transactions on, vol. 8, no. 5, pp. 714-727, Sept.-Oct. 2011
  • 23. Makris, Y; Bayraktaroglu, I.; Orailoglu, A., "Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test", Reliability, IEEE Transactions on, vol. 53, no. 2, pp. 269- 278, June 2004
  • 24. Karimi, N.; Maniatakos, M.; Jas, A.; Tirumurti, C.; Makris, Y, "Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor", Computers, IEEE Transactions on, vol. 60, no. 9, pp. 1274,1287, Sept. 2011
  • 25. Li, Y; Makar, S.; Mitra, S, "CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns", Design, Automation and Test in Europe, 2008. DATE '08 , pp. 885,890, 10-14 March 2008
  • 26. Khedhiri, C.; Karmani, M.; Hamdi, B.; KaLok Man, "Concurrent Error Detection Adder Based on Two Paths Output Computation", Parallel and Distributed Processing with Applications Workshops (ISPAW), 2011 Ninth IEEE International Symposium on, pp. 27,32, May 2011
Typ dokumentu
Bibliografia
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