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2013 | 05 |
Tytuł artykułu

New hardware engine for new operating systems

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Treść / Zawartość
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
Genetic algorithm is a soft computing method that works on set of solutions. These solutions are called chromosome and the best one is the absolute solution of the problem. The main problem of this algorithm is that after passing through some generations, it may be produced some chromosomes that had been produced in some generations ago that causes reducing the convergence speed. From another respective, most of the genetic algorithms are implemented in software and less works have been done on hardware implementation. Our work implements genetic algorithm in hardware that doesn’t produce chromosome that have been produced in previous generations. In this work, most of genetic operators are implemented without producing iterative chromosomes and genetic diversity is preserved. Genetic diversity causes that not only don’t this algorithm converge to local optimum but also reaching to global optimum. Without any doubts, proposed approach is so faster than software implementations. Evaluation results also show the proposed approach is faster than hardware ones.
Wydawca
-
Rocznik
Tom
05
Opis fizyczny
p.16-26,fig.,ref.
Twórcy
autor
  • Department of Computer Science, Islamic Azad University, Ghorveh Branch, Ghorveh, Iran
autor
  • Department of Computer Science, Islamic Azad University, Mianeh Branch, Mianeh, Iran
Bibliografia
  • [1] Fariborz Ahmadi, Amir Shikh Ahmadi, Intenational Journal of Computer Applications 32(10) (2011) 46-50.
  • [2] Fariborz Amadi, Reza Tati, New hardware engine for genetic algorithm, In Proc 5th International Conference on Genetic and Evolutionary Computing, 2012
  • [3] Liu J., A general purpose hardware implementation of genetic algorithms, MSc. Thesis, University of North Carolina, 1993.
  • [4] Scott S. D., Samal A., Seth S., HGA: a hardware-based genetic algorithm, In Proc. ACM/SIGDA 3rd. International Symposium in Field-Programmable Gate Array, pp. 53-59, 1995.
  • [5] Turton B. H., Arslan, T., A parallel genetic VLSI architecture for combinatorial real-time applications – disc scheduling, In Proc. IEE/IEEE International Conference on genetic Algorithms in Engineering Systems, pp. 88-93, 1994.
  • [6] Bland I. M., Megson G. M., Implementing a generic systolic array for genetic algorithms. In Proc. 1st. On-Line Workshop on Soft Computing, pp 268-273, 1996.
  • [7] Megson G. M., Bland I. M., Synthesis of a systolic array genetic algorithm. In Proc. 12th. International Parallel Processing Symposium, pp. 316–320, 1998.
  • [8] D. C. Goldberg. Genic algorithm in search, optimization, and machine learning. Addison Welsey, 1989.
  • [9] Gaines B. R., Advances in Information Systems Science 2 (1969) 37-172.
  • [10] Nedjah, N., Mourelle, L.M., Lecture Notes in Computer Science 2687 (2003)17-24.
  • [11] Bade S. L. M., Hutchings B. L., FPGA-Based Stochastic Neural Networks – Implementation, IEEE Workshop on FPGAs for Custom Computing Machines, Napa Ca, April 10-13, pp. 189-198, 1994.
  • [12] Brown B. D., Card H. C., IEEE Transactions on Computers 50(9) (2001) 891-905.
  • [13] Xilinx, http://www.xilinx.com/, 2004.
  • [14] Michalewics Z., Genetic algorithms + data structures = evolution programs, Springer-Verlag, Berlin, Second Edition, 1994.
  • [15] Scott S. D., Seth S., Samal A., A hardware engine for genetic algorithms, Technical Report, UNL-CSE-97-001, University of Nebraska-Lincoln, July 1997.
  • [16] N. Nedjah, Pararllel evolutionary computations, Springer 2006.
Typ dokumentu
Bibliografia
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