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EN
A novel approach to a trigger mode in the Gas Electron Multiplier (GEM) detector readout system is presented. The system is already installed at WEST tokamak. The article briefly describes the architecture of the GEM detector and the measurement system. Currently the system can work in two trigger modes: Global Trigger and Local Trigger. All trigger processing blocks are parts of the Charge Signal Sequencer module which is responsible for transferring data to the PC. Therefore, the article presents structure of the Sequencer with details about basic blocks, theirs functionality and output data configuration. The Sequencer with the trigger algorithms is implemented in an FPGA chip from Xilinx. Global Trigger, which is a default mode for the system, is not efficient and has limitations due to storing much data without any information. Local trigger which is under tests, removes data redundancy and is constructed to send only valid data, but the rest of the software, especially on the PC side, is still under development. Therefore authors propose the trigger mode which combines functionality of two existing modes. The proposed trigger, called Zero Suppression Trigger, is compatible with the existing interfaces of the PC software, but is also capable to verify and filter incoming signals and transfer only recognized events. The results of the implementation and simulation are presented.
EN
The validation of the measurements quality after on-site diagnostic system installation is necessary in order to provide reliable data and output results. This topic is often neglected or not discussed in detail regarding measurement systems. In the paper recently installed system for soft X-ray measurements is described in introduction. The system is based on multichannel GEM detector and the data is collected and sent in special format to PC unit for further postprocessing. The unique feature of the system is the ability to compute final data based on raw data only. The raw data is selected upon algorithms by FPGA units. The FPGAs are connected to the analog frontend of the system and able to register all of the signals and collect the useful data. The interface used for data streaming is PCIe Gen2 x4 for each FPGA, therefore high throughput of the system is ensured. The paper then discusses the properties of the installation environment of the system and basic functionality mode. New features are described, both in theoretical and practical approach. New modes correspond to the data quality monitoring features implemented for the system, that provide extra information to the postprocessing stage and final algorithms. In the article is described also additional mode to perform hardware simulation of signals in a tokamak-like environment using FPGAs. The summary describes the implemented features of the data quality monitoring features and additional modes of the system.
PL
Niniejszy artykuł prezentuje system do symulacji i analizy stanu pól komutacyjnych. Główną cechą systemu jest to, że obliczenia saą realizowane w dedykowanych układach sprzętowych. Jako moduły obliczeniowe wykorzystane zostały moduł z programowalnym układem FPGA -Spartan-3 firmy Xilinx. Kilkanaście takich modułów zostało połączonych w szeregowy systemi pracuą˛pod kontrolą aplikacji www, która komunikuje się z węzłami obliczeniowymi za pośrednictwem Raspberry Pi, który to realizuje funkcjonalność proxy między typowym oprogramowaniem a programowalnymi układami sprzętowymi.
EN
In this paper there is presented a system for simulations realized in hardware. The subject are blocking states in optical switching fabrics. Model of such a fabric is presented, and the way of its analysis is described. FPGA Spartan-3 chips are used for fast calculations, Raspberry PI, small PC, is used as an interface between PC and electronic part of the system. System is dedicated for searching blocking states (which is realized in hardware) and their analysis (which is realized by GUI and software on PC). Main elements of system are:Web based GUI, scripts and database for storing results, subsystem for controlling FPGA chips (controller is realized on Raspberry PI and its GPIOs) and 18 (or more) FPGA modules as a calculating engines.
PL
Przedstawiono koncepcję i realizację sprzętowo-programowego akceleratora algorytmu Argon2d. Algorytm ten został wykorzystany w części kryptowalut z tego względu, że jego zastosowanie utrudnia realizację bardziej efektywnych obliczeń na GPU w porównaniu z procesorami x86. Autorzy przedstawili i omówili wyniki testów porównania realizacji czysto programowej z wynikami uzyskanymi z użyciem akceleratora.
EN
The paper presents the concept and implementation of the hardware-software accelerator of the Argon2d algorithm. This algorithm was used in some cryptocurrencies because its use hinders the implementation of more efficient calculations on the GPU compared to x86 processors. The authors presented and discussed the results of tests comparing software implementation with the results obtained using the accelerator.
5
Content available remote Waveform-reconfigurable emitter design for multi frequency electrical tomography
EN
In this work we present a design of a multi-frequency electrical tomography (ET) data acquisition device focused on reconfiguration of the emitter for on-line customization of excitation signals. The design is conceived to acquire data for in vivo medical monitoring. This device is implemented using FPGA for real-time data acquisition and a microcontroller SoC that enables internet of things capabilities for further escalation of the device functionality. The ET device allow the study of frequency responses and the generation of customized excitation signals.
PL
W niniejszej pracy przedstawiamy projekt urządzenia do akwizycji danych z wieloczęstotliwościowej tomografii elektrycznej (ET), którego celem jest rekonfiguracja emitera w celu dostosowania sygnałów wzbudzenia w trybie online. Projekt ma na celu pozyskiwanie danych do monitorowania medycznego in vivo. Urządzenie zostało zaimplementowane przy użyciu FPGA do akwizycji danych w czasie rzeczywistym oraz mikrokontrolera SoC, w celu dalszego zwiększenia funkcjonalności urządzenia. Urządzenie ET umożliwia badanie odpowiedzi częstotliwościowych i generowanie niestandardowych sygnałów pobudzających.
6
Content available remote Sprzętowa implementacja nieregularnego dekodera QC-LDPC w strukturze FPGA
PL
W pracy przedstawiono sprzętowa˛ implementacje˛ dekodera kodów QC-LDPC w strukturze FPGA. Zaprezentowany dekoder może być skonfigurowany do obsługi algorytmu Min-Sum lub Normalized Min-Sum. Normalizacje˛ w algorytmie Normalized Min-Sum wykonano za pomoca˛ układów kombinacyjnych. Przedstawiono również porównanie dekoderów o różnych rozmiarach magistral propagacji wiadomości (ang. beliefs). Badania eksperymentalne prowadzono z wykorzystaniem układu FPGA rodziny Cyclone V firmy Intel oraz kodów LDPC ze standardów 802.11ad i 802.16e.
EN
The paper presents hardware implementation of QC-LDPC decoder (Quasi-Cyclic Low-density Parity-Check) in FPGA structure. In the presented decoder, Min-Sum and Normalized Min-Sum algorithms can be utilized. Normalization in the Normalized Min-Sum algorithm is performed using LookUp Tables (LUTs). a comparison of decoder operating with different data bus sizes is also shown. All presented results were obtained in the Intel Cyclone V system for 802.11ad (WiGig) and 802.16e (WiMax) standards.
EN
This paper proposes a novel hybrid software/hardware system to automatically create filters for image processing based on genetic algorithms and mathematical morphology. Experimental results show that the hybrid system, implemented using a combination of a NIOS-II processor and a custom hardware accelerator in an Altera FPGA device, is able to generate solutions that are equivalent to the software version in terms of quality in approximately one third of the time.
PL
W artykule zaproponowano nowe hybrydowe oprogramowanie do automatycznego tworzenia filtrów grafiki bazuj ˛acych na algorytmach genetycznych i morfologii matematycznej. Eksperymenty wykazały ˙ze proponowany system wykorzystuj ˛acy procesor NIOS-II i Altera FPGA jest w stanie generowa´c rozwi ˛azanie niemal trzy razy szybciej ni˙z dotychczas stosowane systemy.
EN
This paper presents a Hardware-In-the-Loop (HIL) co-simulation of SPWM generator for variable speed AC motor drive. This approach allows us to connect the physical FPGA development board that implements the Sine Pulse Width Modulation (SPWM) generator to the Matlab/Simulink environment software in which the power part composed of an inverter and an AC motor is modeled. The HIL co-simulation benefits from the powerful features of the FPGA board in generating PWM pulses at high switching frequencies, and on other side, it gains from the Simulink tools in giving more flexibility and freedom in order to perform different functional tests without any risk that can be happen in case of experimental tests. Detailed co-simulation and experimental results of the AC motor variable speed drive are successfully achieved, showing that the user can run the AC motor at any desired speed.
PL
W artykule przedstawiono symulację sprzętową w pętli (HIL) generatora SPWM do napędu AC o zmiennej prędkości. Takie podejście pozwala nam podłączyć fizyczną płytkę rozwojową FPGA, która implementuje generator modulacji szerokości impulsu sinusoidalnego (SPWM) z oprogramowaniem środowiska Matlab / Simulink, w którym modeluje się część mocy złożoną z falownika i silnika prądu przemiennego. Kosymulacja HIL korzysta z funkcji płyty FPGA w generowaniu impulsów PWM przy wysokich częstotliwościach przełączania, a z drugiej strony zyskuje dzięki narzędziom Simulink, zapewniając większą elastyczność i swobodę w celu wykonywania różnych testów funkcjonalnych bez żadnego ryzyka może się to zdarzyć w przypadku testów eksperymentalnych. Z powodzeniem uzyskano szczegółową współsymulację i wyniki eksperymentalne przemiennika częstotliwości z silnikiem prądu przemiennego, pokazując, że użytkownik może uruchomić silnik prądu przemiennego z dowolną pożądaną prędkością.
EN
The paper presents results of the high level synthesis of an 1024-point radix-2 FFT processors in Xilinx Vivado FPGA environment. The use of various directives controlling the synthesis process is examined. The results indicate that using the proper set of directives the latency of the processor can be reduced by 95% from about 35k for the default parameters to 1.5k cycles after optimizations.
EN
This paper presents the concept and implementation of an electronic system for a switched-capacitor DC-DC converter with high voltage gain. The converter consists of seven switches, five of which being controlled like high-side type. This paper presents a non-typical bootstrap-based gate-driver system so that the converter can run using a single voltage source. The converter requires a special switching pattern to drive seven switches in a steady state and also during the start-up of the converter and the regulation of the output voltage. Therefore, an FPGA-based digital control system is used with various switching algorithms and protection functions implemented. The presented converter is an autonomic device that taps the energy from the main input. Therefore, the electronic system of the converter is equipped with a self-supply system with a wide range of the input voltage. The parameters of the converter such as voltage gain, voltages and power ranges can be scalable for prospective applications with the proposed control system.
11
Content available Start Acceleration of the Space GPS Receiver
EN
The cold start of the space GPS receiver, i.e. the start without any information about the receiver position, satellite constellation, and time, is complicated by a large Doppler shift of a navigation signal caused by the satellite movement on the Earth orbit. That increases about five times the search space of the navigation signals compared to the standard GPS receiver. The paper investigates a method of the acceleration of the GPS receiver cold start time designed for the pico- and femto-satellites. The proposed method is based on a combination of the paralel search in Doppler frequency and PRN codes and the serial search in code phase delay. It can shorten the cold start time of the GPS receiver operating on LEO orbit from about 300 to 60 seconds while keeping the simplicity of FPGA signal processor and low power consumption. The developed algorithm was successfully implemented and tested in the piNAV GPS receiver. The Energy required for the obtaining of the position fix was reduced five times from 36 on to 7.7 Joules. This improvement enables applications of such receiver for the position determination in smaller satellites like Pocket Cube or femto-satellites with a lower energy budget than the Cube Satellite.
EN
This paper presents the design of a compact protocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices. Implementation of the project aims to delineate word boundaries, provide randomness to the electromagnetic interference (EMI) generated by the electrical transitions, allow for clock recovery and maintain direct current (DC) balance. An orthogonal concatenated coding scheme is used for correcting transmission errors using modified Bose–Chaudhuri–Hocquenghem (BCH) code capable of correcting all single bit errors and most of the double-adjacent errors. As a result all burst errors of a length up to 31 bits, and some of the longer group errors, are corrected within 256 bits long packet. The efficiency of the proposed solution equals 46.48%, as 119 out of 256 bits are fully available to the user. The design has been implemented and tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kit with a data rate of 28.2 Gbps. Sample latency analysis has also been performed so that user could easily carry out calculations for different transmission speed. The main advancement of the work is the use of modified BCH(15, 11) code that leads to high error correction capabilities for burst errors and user friendly packet length.
13
Content available Improving characteristics of LUT-based Mealy FSMs
EN
Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy. The paper proposes a novel technology-dependent design method targeting a decrease in the number of look-up table (LUT) elements and their levels in logic circuits of FPGA-based Mealy FSMs. It produces FSM circuits having three levels of logic blocks. Also, it produces circuits with regular systems of interconnections between the levels of logic. The method is based on dividing the set of internal states into two subsets. Each subset corresponds to a unique part of an FSM circuit. Only a single LUT is required for implementing each function generated by the first part of the circuit. The second part is represented by a multi-level circuit. The proposed method belongs to the group of two-fold state assignment methods. Each internal state is encoded as an element of the set of states and as an element of some of its subsets. A binary state assignment is used for states corresponding to the first part of the FSM circuit. The one-hot assignment is used for states corresponding to the second part. An example of FSM synthesis with the proposed method is shown. The experiments with standard benchmarks are conducted to analyze the efficiency of the proposed method. The results of experiments show that the proposed approach leads to diminishing the number of LUTs in the circuits of rather complex Mealy FSMs having more than 15 internal states. The positive property of this method is a reduction in energy consumption (without any overhead cost) and an increase in operating frequency compared with other investigated methods.
EN
Convolutional neural networks (CNNs) were created for image classification tasks. Shortly after their creation, they were applied to other domains, including natural language processing (NLP). Nowadays, solutions based on artificial intelligence appear on mobile devices and embedded systems, which places constraints on memory and power consumption, among others. Due to CNN memory and computing requirements, it is necessary to compress them in order to be mapped to the hardware. This paper presents the results of the compression of efficient CNNs for sentiment analysis. The main steps involve pruning and quantization. The process of mapping the compressed network to an FPGA and the results of this implementation are described. The conducted simulations showed that the 5-bit width is enough to ensure no drop in accuracy when compared to the floating-point version of the network. Additionally, the memory footprint was significantly reduced (between 85 and 93% as compared to the original model).
15
Content available PLC implementation in the form of a System-on-a-Chip
EN
The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.
PL
Filtrem Blooma nazywamy probabilistyczną strukturę danych o niewielkiej zajętości pamięciowej umożliwiającą szybkie sprawdzenie obecności danego elementu w zbiorze. W ramach artykułu przedstawiono problem sprzętowej implementacji filtru Blooma w oparciu o wyłącznie jedną funkcję skrótu oraz metodologię „one-hashing”. W szczególności przeanalizowano wpływ zwiększania rozmiaru pamięci na zmniejszenie prawdopodobieństwa wystąpienia błędnej odpowiedzi pozytywnej.
EN
This article deals with the problem of hardware implementation of Bloom Filter based on one-hashing approach. Particularly, the dependency between the memory size and false positive ratio is examined.
17
Content available remote Sprzętowa implementacja dekodera LDPC w strukturze FPGA*
PL
W artykule przedstawiono sprzętową implementację dekodera LDPC (ang. Low-Density Parity-Check) w strukturze FPGA (ang. Field Programmable Gate Array). W celu zredukowania złożoności implementacji wykorzystano algorytm MIN-SUM dla węzłów bitowych (CNU) i węzłów kontrolnych (VNU). W zrealizowanym dekoderze wykorzystano kod regularny (3,6) macierzy kontrolnej o wymiarach 512 x 1024 i zaimplementowano 4-bitową magistralę danych. Poprawność działania dekodera zweryfikowano praktycznie.
EN
The article presents the hardware implementation of the LDPC decoder (Low-density parity-check) in the FPGA structure (Field Programmable Gate Array). In order to reduce the complexity of the implementation, the Min-Sum algorithm for bit nodes (CNUs) and control nodes (VNUs) was used. The presented implementation was created using a regular code (3.6) of a 512 x 1024 control matrix. A 4-bit data bus was implement.
EN
Hardware implementation of Shunt Active Power Filter (SAPF) to regulate harmonics in the grid current is presented in this work. Dead-beat controller is employed to regulate the harmonics injected by SAPF using Spartan-6 FPGA processor. The effectiveness of the control strategy is tested under different operating conditions through MATLAB simulations and experimental approach to reduce the grid current harmonics and to meet the IEEE519:2014 recommendations for harmonic regulation guidelines, at the Point-of-Common-Coupling(PCC).
PL
Zaprezentowano bocznikowy filtr aktywny zaprojektowany do redukcji harmonicznych w sieci. Sterownik typu dead-beat jest zastosowany wstrzykiwania prądu z wykorzystaniem procesora Spartan-6 FPGA. Zbadano efektywność sterownia w różnych warunkach pracy przy spełnieniu rekomendacji IEEE519:2014.
19
Content available remote Implementation of the Proportional Resonant controller in the FPGA system
EN
The article presents the process of discretization and implementation of the Proportional Resonant controller in a digital programmable system of FPGA type. The synthesis of the regulator in a continuous version is presented and on its basis the discretization has been carried out. The digital form of the regulator has been implemented into the FPGA system. The device has been simulated in real time and this paper presents some of the results of this research. Its aim was to evaluate the operation of the regulator in a digital form, prior to the implementation into a real device. The article is a continuation of the research aimed at the implementation of the regulator in the real device.
PL
W artykule przedstawiono proces dyskretyzacji i implementacji regulatora P+R w cyfrowym układzie programowalnym typu FPGA. Zaprezentowano syntezę regulatora w wersji ciągłej i na jej podstawie przeprowadzono dyskretyzację. Cyfrowa postać regulatora została zaimplementowana do układu FPGA. Przeprowadzona została symulacja urządzenia w czasie rzeczywistym a niniejsza praca prezentuje niektóre wyniki tych badań. Jej celem była ocena pracy regulatora w cyfrowej postaci, przed implementacją do rzeczywistego urządzenia. Artykuł jest kontynuacją badań zmierzających do uruchomienia regulatora w rzeczywistym urządzeniu.
PL
W artykule zaprezentowano projekt architektury oraz sprzętową implementację toru przetwarzania obrazu dedykowanego do wykrywania przewodów napowietrznych w czasie rzeczywistym. Detekcję przewodów zaimplementowano w postaci potokowej procedury sprzętowej przy użyciu algorytmów wykrywania krawędzi, a następnie ich redukcji. Projekt przetestowano w środowisku FPGA Intel Cyclone V. Przeanalizowano opóźnienia i złożoność sprzętową zsyntezowanej struktury w FPGA. Oszacowano również maksymalną szybkość przetwarzania obrazu z użyciem zaproponowanej implementacji.
EN
The paper presents the architecture design and hardware implementation of a custom image processing module dedicated for detection of high voltage lines in real time. It has been implemented in the form of a pipelined hardware procedure using edge detection and reduction algorithm. The design was tested in the Intel Cyclone V FPGA environment. Time and hardware complexity of the synthesized structure in FPGA were analyzed. The maximum image processing speed was also estimated using the proposed implementation.
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