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1

VSTM – nowoczesny zaawansowany wizyjny system pomiarowy – realizacyjne bariery technologiczne

Kusiak Markus, Papuga-Szałapski Jakub

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

|

2025

|

nr 2

20--24

PL

Artykuł przedstawia innowacyjny system pomiarowy VSTM (Visual Stop Time Meter), znany komercyjnie jako ELOStopTime, wykorzystywany do bezkontaktowego pomiaru czasu zatrzymania maszyn i wyznaczenia minimalnej odległości technicznego środka ochronnego od niebezpiecznego ruchu maszyny. Tradycyjne metody, bazujące na enkoderach impulsowych, ograniczone są do ruchów prostoliniowych, co czyni je nieprzydatnymi w przypadku bardziej skomplikowanych trajektorii ruchu. VSTM rozwiązuje ten problem dzięki zastosowaniu technologii wizyjnej i przetwarzania obrazu w czasie rzeczywistym, umożliwiając dokładne pomiary nawet w trudnych warunkach przemysłowych. W artykule omówiono wyzwania technologiczne, takie jak wybór odpowiednich kamer, zapewnienie wysokiej rozdzielczości i dokładności czasowej na poziomie 1 ms, a także optymalizację algorytmów analizy obrazu. System VSTM został opracowany przez firmę ELOKON, dzięki wsparciu Narodowego Centrum Badań i Rozwoju, a obecnie jest wdrażany na rynku.

EN

The article presents an innovative measurement system, VSTM (Visual Stop Time Meter), commercially known as ELOStopTime, used for non-contact measurement of machine stop time and determination of the minimum distance of a technical protective device from the hazardous movement of the machine. Traditional methods based on impulse encoders are limited to linear movements, making them ineffective for complex motion trajectories. VSTM overcomes this limitation by utilizing vision technology and real-time image processing, even in challenging industrial environments, allowing for precise measurements. The article discusses technological challenges, such as selecting appropriate cameras, ensuring high resolution and temporal accuracy at the 1 ms level, and optimizing image analysis algorithms. ELOKON developed the VSTM system with support from the National Centre for Research and Development and is currently being implemented in the market.

2

Optical control system for quantum bit emulator based on green laser, AOM modulators and FPGA technology

Długopolski Jacek, Życzkowski Marek, Pakuła Anna, Fiderkiewicz Szymon, Sobotka Piotr, Suleja Wawrzyniec, Sadowski Marcin

Opto-Electronics Review

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2025

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Vol. 33, No. 4

art. no. e157332

EN

Scientists involved in building quantum computers are currently facing many physical difficulties. Creating qubits, manipulating them and reading their state requires a lot of experience. This paper describes an optical laser system as a test platform for quantum-optical control that enables effective manipulation of an emulated quantum bit. Importantly, it is a reproduction of the system controlling the optical path in real ion traps. This solution makes it possible to study the phenomena occurring in such systems and to learn about the wide range of problems that a designer and an operator of quantum systems may encounter, even before they start building them. The optical system presented in the article uses, among others, a 532 nm laser, acousto-optic modulators (AOMs), ultrafast light detectors, and a programmable FPGA chip. The entire optical system was then attached to the QUBIT emulator and thoroughly tested. The article describes the design and operation of the proposed optical system and shows an example of how to control it using a Python script.

3

FPGA-based Low Latency Square Root CORDIC Algorithm

Węgrzyn Mariusz, Voytusik Stepan, Gavkalova Natalia

Journal of Telecommunications and Information Technology

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2025

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nr 1

21--29

EN

The coordinate rotation digital computer (CORDIC) algorithm is a popular method used in many fields of science and technology. Unfortunately, it is a time-consuming process for central processing units (CPUs) and graphics processing units (GPUs), and even for specialized digital signal processing (DSP) solutions. The CORDIC algorithm is an alternative for Newton-Raphson numerical calculation and for the FPGA based resource-expensive look-up-table (LUT) method. Various modifications of the CORDIC algorithm allow to speed up the operation of hardware in edge computing devices.With that context taken into consideration, this article presents a fast and accurate square root floating point (SQRT FP) CORDIC function which can be implemented in field programmable gate arrays (FPGAs). The proposed algorithm offers low-complexity, decent accuracy and speed, and is sufficient for digital signal processing (DSP) applications, such as digital filters, accelerators for neural networks, machine learning and computer vision applications, and intelligent robotic systems.

4

PyHLS: Intermediate Representation for Versatile High-Level Synthesis

Cieszewski Radoslaw

International Journal of Electronics and Telecommunications

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2025

|

Vol. 71, No. 4

37

EN

High-Level Synthesis (HLS) has become an established methodology to accelerate the development of FPGA-based systems by allowing algorithms to be written in high-level languages (HLLs) such as C/C++ or Python. Yet, for real-time physics experiments—including fusion plasma diagnostics, high-energy physics (HEP) detectors, and rare-event astrophysical triggers—conventional HLS still falls short in three essential aspects: determinism, portability, and auditability. Pragmas embedded in HLL code blur the separation between algorithmic intent and implementation details, coupling scientific software to a particular device or compiler version. This is particularly problematic in long-lived scientific projects such as ITER or the Pierre Auger Observatory, where systems must remain functional and maintainable over decades [4]-[6]. To address these challenges, we propose an Intermediate Representation (IR)-centric HLS flow—PyHLS—that explicitly introduces an abstraction layer between algorithm and Register-Transfer Level (RTL) design. The IR centralizes all performance-critical aspects: timing contracts (initiation interval, latency, jitter), concurrency (loop unrolling, pipelining), memory layout (banking, tiling, port allocation), and resource binding (DSPs, BRAMs, AI tiles). In this model, the algorithm is expressed in clean, testable Python code [1], [2], while device-specific optimizations are described in a structured IR graph. This IR is then lowered into a reusable VHDL microinstruction library [3], which serves as a portable middle layer across devices. By ver-sioning and auditing IR graphs and instruction streams, PyHLS ensures reproducibility and traceability—critical properties in scientific computing where results must be verifiable years after deployment. The methodology builds upon earlier work in Python-based high-level synthesis, parameterizable metamodels, and algorithmic synthesis with multi-level compilers [8], [9], [11]. It in-corporates systematic design space exploration (DSE), allowing parameter sweeps over IR attributes and early feasibility checks. The flow is complemented by a cycle-accurate microinstruction emulator, which validates both functionality and timing contracts before vendor toolchains are invoked, reducing iteration time and catching infeasible designs early. We demonstrate the motivation and applicability of this approach in two demanding domains. First, in plasma diagnostics at JET/ITER, where spectrometer and data acquisition systems must combine high bandwidth with deterministic latency [6]. Second, in trigger pipelines for astroparticle physics, where artificial neural networks (ANNs) and fuzzy-logic algorithms have been implemented directly in FPGA logic to discriminate rare events from large backgrounds [4], [5]. These use-cases highlight the need for explicit IR-level contracts and modularity: the same high-level algorithm must be portable across device generations, yet adapted to exploit specialized hardware resources such as DSP slices, systolic AI engines, or high-bandwidth memories. The contribution of this work is therefore threefold: 1) We formalize the role of an explicit IR in HLS, decoupling algorithms from implementation decisions and introducing contract-driven determinism. 2) We present a reusable VHDL microinstruction library and emulator that stabilize implementation and provide auditable artifacts. 3) We show how PyHLS extends naturally to heterogeneous FPGAs, mapping operators to emerging AI/ML blocks while maintaining scientific reproducibility and portability across decades. By unifying algorithmic specification, IR-based parameterization, and reusable microinstructions, PyHLS establishes a sustainable methodology for real-time physics experiments and beyond. In short: write the science once, retarget the hardware many times.High-Level Synthesis (HLS) has become an established methodology to accelerate the development of FPGA-based systems by allowing algorithms to be written in high-level languages (HLLs) such as C/C++ or Python. Yet, for real-time physics experiments—including fusion plasma diagnostics, high-energy physics (HEP) detectors, and rare-event astrophysical triggers—conventional HLS still falls short in three essential aspects: determinism, portability, and auditability. Pragmas em-bedded in HLL code blur the separation between algorithmic intent and implementation details, coupling scientific software to a particular device or compiler version. This is particularly problematic in long-lived scientific projects such as ITER or the Pierre Auger Observatory, where systems must remain functional and maintainable over decades [4]-[6]. To address these challenges, we propose an Intermediate Representation (IR)-centric HLS flow—PyHLS—that explicitly introduces an abstraction layer between algorithm and Register-Transfer Level (RTL) design. The IR centralizes all performance-critical aspects: timing contracts (initiation interval, latency, jitter), concurrency (loop unrolling, pipelining), memory layout (banking, tiling, port allocation), and resource binding (DSPs, BRAMs, AI tiles). In this model, the algorithm is expressed in clean, testable Python code [1], [2], while device-specific optimizations are described in a structured IR graph. This IR is then lowered into a reusable VHDL microinstruction library [3], which serves as a portable middle layer across devices. By versioning and auditing IR graphs and instruction streams, PyHLS ensures reproducibility and traceability—critical properties in scientific computing where results must be verifiable years after deployment. The methodology builds upon earlier work in Python-based high-level synthesis, parameterizable metamodels, and algorithmic synthesis with multi-level compilers [8], [9], [11]. It in-corporates systematic design space exploration (DSE), allowing parameter sweeps over IR attributes and early feasibility checks. The flow is complemented by a cycle-accurate microinstruction emulator, which validates both functionality and timing contracts before vendor toolchains are invoked, reducing iteration time and catching infeasible designs early. We demonstrate the motivation and applicability of this approach in two demanding domains. First, in plasma diagnostics at JET/ITER, where spectrometer and data acquisition systems must combine high bandwidth with deterministic latency [6]. Second, in trigger pipelines for astroparticle physics, where artificial neural networks (ANNs) and fuzzy-logic algorithms have been implemented directly in FPGA logic to discriminate rare events from large backgrounds [4], [5]. These use-cases highlight the need for explicit IR-level contracts and modularity: the same high-level algorithm must be portable across device generations, yet adapted to exploit specialized hardware resources such as DSP slices, systolic AI engines, or high-bandwidth memories. The contribution of this work is therefore threefold: 1) We formalize the role of an explicit IR in HLS, decoupling algorithms from implementation decisions and introducing contract-driven determinism. 2) We present a reusable VHDL microinstruction library and emulator that stabilize implementation and provide auditable artifacts. 3) We show how PyHLS extends naturally to heterogeneous FPGAs, mapping operators to emerging AI/ML blocks while maintaining scientific reproducibility and portability across decades. By unifying algorithmic specification, IR-based parameterization, and reusable microinstructions, PyHLS establishes a sustainable methodology for real-time physics experiments and beyond. In short: write the science once, retarget the hardware many times. H

5

Hardware implementation of MBFSK modulation technique for underwater wireless communications

Pilarski Rafał, Wojewódka Łukasz

International Journal of Electronics and Telecommunications

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2025

|

Vol. 71, No. 4

2

EN

The underwater communication technique based on MBFSK (Multiple Binary Frequency Shift Keying) modulation is used in challenging propagation conditions. Despite the band-width limitations present underwater, it provides stable underwa-ter connectivity. This paper presents a hardware implementation of the MBFSK modulation technique for underwater wireless communications. The implementation was carried out using an FPGA-based programmable logic device. The concept of the device design, the hardware solution, and the firmware descrip-tion are presented. An overview and diagram of the underwater communication system are also provided. The transceiver system was tested in the tank of the Hydroacoustics Laboratory of the Gdynia Maritime University, and the results are presented and discussed. The aim of this work is to present the design, software algorithm, and test results of the developed underwater communication system.

6

FPGA implementation of normalized correlation function

Mroczek Krzysztof

International Journal of Electronics and Telecommunications

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2025

|

Vol. 71, No. 3

20

EN

Correlation analysis is a frequently used tool in signal detection and classification tasks. This paper presents the design and FPGA implementations of a hardware module for calculating the Pearson correlation coefficient. This module is designed for use in signal template matching, where a measurement signal is correlated with a template. It has been described in Verilog and implemented on Intel Cyclone V FPGA. The module consists of two main parts, which are: a correlation filter and normalization modules. Correlation filters performing the calculation in the time domain and in the frequency domain are described. The project has been verified in simulation using ModelSim and checked on hardware. As a result of this work, hardware IP cores are developed enabling parametrization and programming in data word-lengths, filter size, calculation speed, FFT/IFFT size, length, and number of processing templates. Developed resources are intended to be used in FPGA-based hardware, e.g. DAQ systems, working with sampling frequencies from kHz to above 130 MHz.

7

IoTsystem with frequency converters of physical quantities on FPGA

Osadchuk Oleksandr V., Osadchuk Iaroslav O., Skoshchuk Valentyn

Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska

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2025

|

T. 15, nr 3

59--66

EN

The paper presents an IoT system that ensures efficient collection, processing, and transmission of measurements from multichannel radio engineering systems based on FPGA. The developed system is designed for use in remote and hard-to-reach locations, where precision, reliability,and energy efficiency are critical. The implementation integrates the LilyGo LoRa32 module, which supports modern wireless communication protocols such as LoRa, WiFi, and Bluetooth. The core of data transmission is the compact CBOR format, which minimizes the volume of transmitted dataand delays. The system includes a LoRa hub capable of receiving data from numerous collection devices, consolidatingthem into a centralized point,and transmitting them to a server via a WiFi connection. On the server side, a REST API has been developed based on the FastAPI framework, allowing the receipt of data in CBOR format, processing it, and storing it in an SQLite database. The use of the HTTPS protocol ensures the security of transmitted data, including confidentiality, authenticity, and integrity. The server also provides clients with access to data through multiple API interfaces, facilitating easy integrationwith other systems. A mobile application was separately developed using Kotlin and Android Studio, providing convenient accessto the collected measurements. The application supports real-time dynamic data updates, allowing users to monitor connection status, select hubsand collection devices, as well as analyze and visualize the received results. The developed IoT system demonstrates high performance and versatility, making it suitable for a wide range of applications, including industrial automation, environmental monitoring, agriculture, and other IoT scenarios. Further development of this system includes improving data processing algorithms, increasing the hub's throughput capacity, and expanding functionality for real-time monitoring. This paves the way for the creation of innovative IoT solutions capable of meeting the demands of modern technologies in various fields.

PL

Artykuł przedstawia system IoT, który zapewnia wydajne gromadzenie, przetwarzanie i transmisję pomiarów z wielokanałowych systemów radiotechnicznych opartych na FPGA. Opracowany system jest przeznaczony do stosowania w odległych i trudno dostępnych lokalizacjach, gdzie kluczowe znaczenie mają precyzja, niezawodność i efektywność energetyczna. Implementacja integruje moduł LilyGo LoRa32, któryobsługuje nowoczesne protokoły komunikacji bezprzewodowej, takie jak LoRa, WiFi i Bluetooth. Podstawą transmisji danych jest kompaktowy format CBOR, który minimalizuje objętość przesyłanych danych i opóźnienia. System zawiera koncentrator LoRa zdolny do odbierania danych z wielu urządzeń zbierających, konsolidowania ich w scentralizowanym punkcie i przesyłania do serwera za pośrednictwem połączenia WiFi. Po stronie serwera opracowano interfejs API REST oparty na frameworku FastAPI, umożliwiający odbiór danych w formacie CBOR, przetwarzanie ich i przechowywanie w bazie danych SQLite. Zastosowanie protokołu HTTPS zapewnia bezpieczeństwo przesyłanych danych, w tym poufność, autentyczność i integralność. Serwer zapewnia również klientom dostęp do danych poprzez wiele interfejsów API, ułatwiając integrację z innymi systemami. Oddzielnie opracowano aplikację mobilną przy użyciu Kotlin i Android Studio, zapewniającą wygodny dostęp do zebranych pomiarów. Aplikacja obsługuje dynamiczne aktualizacje danych w czasie rzeczywistym, umożliwiając użytkownikom monitorowanie stanu połączenia, wybór hubów i urządzeń zbierających dane, a także analizę i wizualizację otrzymanych wyników. Opracowany system IoT charakteryzuje się wysoką wydajnością i wszechstronnością, dzięki czemu nadaje siędo szerokiego zakresu zastosowań, w tym automatyki przemysłowej, monitorowania środowiska, rolnictwa i innych scenariuszy IoT. Dalszy rozwój tego systemu obejmuje ulepszenie algorytmów przetwarzania danych, zwiększenie przepustowości koncentratora oraz rozszerzenie funkcjonalności monitorowania w czasie rzeczywistym. Otwiera to drogę do tworzenia innowacyjnych rozwiązań IoT, które są w stanie sprostać wymaganiom nowoczesnych technologii w różnych dziedzinach.

8

VSTM : nowoczesny zaawansowany wizyjny system pomiarowy : realizacyjne bariery technologiczne

Kusiak Markus, Papuga-Szałapski Jakub

Elektronika : konstrukcje, technologie, zastosowania

|

2025

|

Vol. 66, Nr 3

2--6

PL

Artykuł przedstawia innowacyjny system pomiarowy VSTM (Visual Stop Time Meter), znany komercyjnie jako ELOStopTime, wykorzystywany do bezkontaktowego pomiaru czasu zatrzymania maszyn i wyznaczenia minimalnej odległości technicznego środka ochronnego od niebezpiecznego ruchu maszyny. Tradycyjne metody, bazujące na enkoderach impulsowych, ograniczone są do ruchów prostoliniowych, co czyni je nieprzydatnymi w przypadku bardziej skomplikowanych trajektorii ruchu. VSTM rozwiązuje ten problem dzięki zastosowaniu technologii wizyjnej i przetwarzania obrazu w czasie rzeczywistym, umożliwiając dokładne pomiary nawet w trudnych warunkach przemysłowych. W artykule omówiono wyzwania technologiczne, takie jak wybór odpowiednich kamer, zapewnienie wysokiej rozdzielczości i dokładności czasowej na poziomie 1 ms, a także optymalizację algorytmów analizy obrazu. System VSTM został opracowany przez firmę ELOKON, dzięki wsparciu Narodowego Centrum Badań i Rozwoju, a obecnie jest wdrażany na rynku.

EN

The article presents an innovative measurement system, VSTM (Visual Stop Time Meter), commercially known as ELOStopTime, used for non-contact measurement of machine stop time and determination of the minimum distance of a technical protective device from the hazardous movement of the machine. Traditional methods based on impulse encoders are limited to linear movements, making them ineffective for complex motion trajectories. VSTM overcomes this limitation by utilizing vision technology and real-time image processing, even in challenging industrial environments, allowing for precise measurements. The article discusses technological challenges, such as selecting appropriate cameras, ensuring high resolution and temporal accuracy at the 1 ms level, and optimizing image analysis algorithms. ELOKON developed the VSTM system with support from the National Centre for Research and Development and is currently being implemented in the market.

9

Implementation of a Cost-Effective, Accurate Photoacoustic Imaging SystemBased on High-Power LED Illumination and FPGA-Based Circuitry

Ahangar Darband Maryam, Najafiaghdam Esmaeil

Archives of Acoustics

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2025

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Vol. 50, nr 1

107--114

EN

Imaging based on the photoacoustic (PA) phenomenon is a type of hybrid imaging approach that combinesthe advantages of pure optical and pure acoustic imaging, achieving good results. This method, which offershigh resolution, suitable contrast, and non-ionizing radiation, is valuable for the early detection of various typesof cancer. Recently, multiple studies have focused on improving different components of this imaging system. Inthis presentation, we implemented a simplest form of a PA imaging system for detecting blood vessels, given thatangiogenesis is recognized as a common symptom of many cancers. For the first time, we implemented a high-power light-emitting diode (LED), to replace bulky and expensive lasers, and integrated circuit technologiessuch as field-programmable gate arrays (FPGAs) for a simple LED driver circuit and data acquisition (DAQ).Using an FPGA block, we successfully generated a 200-ns square pulse wave with a repetition frequency of25 kHz, whose amplified form can drive a high-power LED at 1050 nm for appropriately stimulating the sample.By using ultrasonic sensors with a central frequency of 1 MHz and a DAQ system with 16-bit accuracy, alongwith a suitable algorithm for image reconstruction, we successfully detected blood vessels in a breast tissuemimic. With the use of the FPGA-based block, the image reconstruction algorithm was accelerated. Finally,the simultaneous and first-time use of LED and FPGA-based circuit technology for driving the LED, outputinformation processing and image reconstruction were performed in PA imaging.

10

Rozwój i zastosowanie systemu monitoringu urządzeń automatyki przemysłowej SMUAP

Rakowski Franciszek, Ostapowicz Piotr, Stróżyk Maciej, Głowiak Maciej, Smolik Marek

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

|

2024

|

nr 4

77--80

PL

W odpowiedzi na rosnące wyzwania stawiane przedsiębiorstwom produkcyjnym przez rewolucję przemysłową 4.0, w tym zagrożenia atakami cybernetycznymi, opracowany został System Monitoringu Urządzeń Automatyki Przemysłowej (SMUAP). Architektura SMUAP oparta jest na pasywnym monitorowaniu ruchu sieciowego oraz analizie komunikacji między urządzeniami. Moduł analityczny systemu oparty jest głównie na sztucznej inteligencji i uczeniu maszynowym, natomiast narzędziem do monitorowania sieci jest pasywny sniffer (w kilku opcjach, włączając technologię FPGA).

EN

In response to the growing challenges faced by manufacturing enterprises due to the Industry 4.0 revolution, including the threat of cyber attacks, the Industrial Automation Monitoring System (SMUAP) has been developed. The architecture of SMUAP is based on passive monitoring of network traffic and analysis of communication between devices. The analytical module of the system is mostly based on artificial intelligence and machine learning, while the network monitoring tool is passive sniffer (in several options, including FPGA technology).

11

System sterowania zasilaniem elektrolizera alkalicznego

Pilarski Rafał, Górecki Krzysztof

Przegląd Elektrotechniczny

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2024

|

R. 100, nr 6

61--65

PL

W pracy przedstawiono opracowany i wykonany system do badania właściwości elektrolizera alkalicznego. Zaprezentowano koncepcję i konstrukcję urządzenia, jego schemat blokowy, opis oprogramowania software procesora wbudowanego NIOS II oraz firmware układu FPGA. Opisano dedykowaną aplikację opracowaną dla środowiska LabVIEW. Przedstawiono wyniki pomiarów ilustrujących wpływ sygnału sterującego na wybrane parametry elektrolizera. Przedyskutowano uzyskane wynik pomiarów.

EN

This paper presents a developed and constructed system for testing the properties of an alkaline electrolyzer. The concept and design of the device, its block diagram, description of the NIOS II embedded processor software and the FPGA firmware are presented. A dedicated LabVIEW application is described. Measurements results illustrating the influence of the control signal on selected electrolyzer parameters are presented. The obtained results of measurements were discussed.

12

FPGA-based three edge detection algorithms (Sobel, Prewitt and Roberts) implementation for image processing

Abdullah Hiba-Allah Tariq, Mahmood Riyadh Zaghlool, Alhaj Zber Sanabel Muhson, Mohammed Rasha A., Ahmed Marwa Riyadh, Talab Azhar Waleed

Przegląd Elektrotechniczny

|

2024

|

R. 100, nr 2

29--33

EN

This technique aims to identify bone boundaries and fractures in noisy images by leveraging information from X-ray images. The computer-aided bone fracture detection method is primarily designed to help doctors generate improved diagnostic reports. Identifying accurate boundaries in noisy images remains challenging. Image processing algorithms have been limited to slow software implementations due to restricted processor speeds, necessitating a dedicated processor for edge detection. The Spartan3E-XC3S1600 FPGA kit will be employed to construct a fast architecture capable of performing edge detection using Sobel, Prewitt and Roberts edge detection systems.

PL

Ta technika ma na celu identyfikację granic kości i złamań na zaszumionych obrazach poprzez wykorzystanie informacji z obrazów rentgenowskich. Wspomagana komputerowo metoda wykrywania złamań kości ma przede wszystkim pomóc lekarzom w generowaniu lepszych raportów diagnostycznych. Identyfikacja dokładnych granic w hałaśliwych obrazach pozostaje wyzwaniem. Algorytmy przetwarzania obrazu zostały ograniczone do powolnych implementacji oprogramowania ze względu na ograniczoną prędkość procesora, co wymagało dedykowanego procesora do wykrywania krawędzi. Zestaw Spartan3E-XC3S1600 FPGA zostanie wykorzystany do zbudowania szybkiej architektury zdolnej do wykrywania krawędzi z wykorzystaniem systemów wykrywania krawędzi Sobel, Prewitt i Roberts.

13

SoC-FPGA based concept of hardware aided quantum simulation

Długopolski Jacek, Czerski Jakub, Knapik Mateusz

Journal of Automation Mobile Robotics and Intelligent Systems

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2024

|

Vol. 18, No. 2

17--23

EN

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field- Programmable Gate Array) enables the delegating of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support the CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows encountered limitations to be overcome and the flexibility known from high-level solutions and high performance achieved with low-level programming to be maintained without the need for a high financial background.

14

Optimized Supervised ML for Medicinal Plant Detection : An FPGA Implementation

Raghukumar Amrutha M., Narayanan Gayathri, Somanathan Geethu Remadevi

International Journal of Electronics and Telecommunications

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2024

|

Vol. 70, No. 3

537--544

EN

Medicinal plants have a huge significance today as it is the root resource to treat several ailments and medical disorders that do not find a satisfactory cure using allopathy. The manual and physical identification of such plants requires experience and expertise and it can be a gradual and cumbersome task, in addition to resulting in inaccurate decisions. In an attempt to automate this decision making, a data set of leaves of 10 medicinal plant species were prepared and the Gray-level Co-occurence Matrix (GLCM) features were extracted. From our earlier implementations of the several machine learning algorithms, the k-nearest neighbor (KNN) algorithm was identified as best suited for classification using MATLAB 2019a and has been adopted here. Based on the confusion matrices for various k values, the optimum k was selected and the hardware implementation was implemented for the classifier on FPGA in this work. An accuracy of 88.3% was obtained for the classifier from the confusion chart. A custom intellectual property (IP) for the design is created and its verification is done on the ZedBoard for three classes of plants.

15

Low-cost ANS encoder for lossless data compression in FPGAs

Pastuła Magdalena, Russek Paweł, Wiatr Kazimierz

International Journal of Electronics and Telecommunications

|

2024

|

Vol. 70, No. 1

219--228

EN

We present the implementation of the hardware ANS compressor in FPGAs. The main goal of the design was to propose a solution suitable to low-cost, low-energy embedded systems. We propose the streaming-rANS algorithm of the ANS family as a target for the implementation. Also, we propose a set of algorithm parameters that substantially reduce the use of FPGA resources, and we examine what is the influence of the chosen parameters on compression performance. Further, we compare our design to the lossless codecs found in literature, and to the streaming-rANS codecs with arbitrary parameters.

16

IR detection module with integrated real-time FIR filter implemented in FPGA

Achtenberg Krzysztof, Mikołajczyk Janusz, Bielecki Zbigniew

International Journal of Electronics and Telecommunications

|

2024

|

Vol. 70, No. 1

175--182

EN

Infrared detectors are usually characterized by 1/f noise when operating with biasing. This type of noise significantly reduces detection capabilities for low-level and slow signals. There are a few methods to reduce the influence of 1/f noise, like filtering or chopper stabilization with lock-in. Using the first one, a simple 1st-order analog low-pass filter built-in amplifier usually cuts off 1/f noise fluctuations at low frequencies. In comparison, the stabilization technique modulates the signal transposing to a higher frequency with no 1/f noise and then demodulates it back (lock-in amplifiers). However, the flexible tuned device, which can work precisely at low frequencies, is especially desirable in some applications, e.g., optical spectroscopy or interferometry. The paper describes a proof-of-concept of an IR detection module with an adjustable digital filter taking advantage of finite impulse response type. It is based on the high-resolution analog-to-digital converter, field-programmable gate array, and digital-to-analog converter. A microcontroller with an implemented user interface ensures control of such a prepared filtering path. The module is a separate component with the possibility of customization and can be used in experiments or applications in which the reduction of noises and unexpected interferences is needed.

17

Advanced High-Level Synthesis techniques based on metamodel

Cieszewski Radoslaw, Romaniuk Ryszard, Poźniak Krzysztof, Linczuk Maciej

International Journal of Electronics and Telecommunications

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2024

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Vol. 70, No. 4

1049-1056

EN

This paper explores advanced techniques in high-level synthesis (HLS) utilizing metamodel structures. Metamodels act as models of hardware models, generating internal hardware models based on parameter inputs and exploring the solution space to find optimal configurations. The focus is on enhancing HLS processes through metamodeling, enabling more efficient hardware design and optimization. Key contributions include a novel metamodel framework and a case study demonstrating its application in complex system designs. The proposed methods show significant improvements in synthesis efficiency and scala-bility, making them highly relevant for modern FPGA and ASIC design workflows.

18

A novel edge computing approach to astronomical image data processing based on sCMOS camera using SoC

Zienkiewicz Paweł, Karpińska Katarzyna, Jamroży Mikołaj, Juszczyk Bartłomiej, Pochapskyi Dmytro, Przedpełski Tomasz, Łukasiewicz Jerzy, Czortek Natalia, Brona Grzegorz

International Journal of Electronics and Telecommunications

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2024

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Vol. 70, No. 2

489--494

EN

The ever-growing deluge of astronomical data challenges traditional server-based processing, hindering real-time analysis and scientific discovery. This paper proposes a novel approach: edge computing directly on an sCMOS camera using a System-on-Chip (SoC) architecture currently developed at Creotech Instruments. We present a custom-designed camera equipped with an FPGA-based SoC, enabling on-board pre-processing and feature extraction of astronomical images. This significantly reduces data transmission, minimizes latency, and empowers real-time decision-making for critical observations. We showcase the camera's capabilities through real-world scenarios, demonstrating its usability in astronomy.

19

Reducing the number of LUTs for Mealy FSMs with state transformation

Barkalov Alexander, Titarenko Larysa, Mielcarek Kamil

International Journal of Applied Mathematics and Computer Science

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2024

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Vol. 34, no. 1

167--178

EN

In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSM circuit is one of the most important characteristics used in logic synthesis. In this paper, a method is proposed which aims at reducing LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks. Under certain conditions, each function for any logic level is represented by a circuit including a single LUT. The proposed approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes into extended state codes). The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of FSM inputs and states.

20

A physical model of quantum bit behavior based on a programmable FPGA integrated circuit

Długopolski Jacek, Sadowski Marcin, Suleja Wawrzyniec

Computer Science

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2024

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T. 25 (4)

499--519

EN

The rapidly developing field of quantum computing and the ongoing lack of widely available quantum computers create the need for scientists to build their simulators. However, mathematical simulation of such circuits usually ignores many aspects and problems found in real quantum systems. In this article, the authors describe a quantum bit emulator based on FPGA integrated circuits. In this case, FPGA technology provides real-time massive parallelism of the modeled physical phenomena. The modeled QUBIT is represented using a Bloch sphere. Its quantum state is set and modified only by precise pulses of an electrical signal, and with the help of similar pulses, it manifests its current state in real time. The constructed QUBIT was additionally equipped with decoherence mechanisms and with circuits that intentionally respond to internal and external noises that distort its current quantum state. This article presents and discusses how such a physically built emulator works.