Wyniki wyszukiwania - BazTech

1

Data analysis system for surface potential of biological tissues

Hyka Oleksii, Vejar Andres, Rymarczyk Tomasz

Przegląd Elektrotechniczny

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2022

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R. 98, nr 5

157--160

EN

A portable low-power monitoring system for measuring surface biopotential and data processing is presented. The small device was designed using hardware and codesign. The system is based on a microcircuit consisting of a field-programmable gate array device and a dual-core microcontroller. The selected reconfigurable hardware provides the desired level of speed and accuracy combined with low power consumption for online data processing applications. Spectroscopy impedance measurements are used to analyze the electrical properties of biological tissue.

PL

Przedstawiono przenośny system monitorowania o niskim poborze mocy do pomiaru biopotencjału powierzchniowego i przetwarzania danych. Małe urządzenie zostało zaprojektowane z wykorzystaniem projektowania sprzętowego i kodowego. System oparty jest na mikroukładzie składającym się z programowalnej matrycy bramek oraz dwurdzeniowego mikrokontrolera. Wybrany rekonfigurowalny sprzęt zapewnia pożądany poziom szybkości i dokładności w połączeniu z niskim zużyciem energii dla aplikacji przetwarzania danych online. Pomiary impedancji w spektroskopii są wykorzystywane do analizy właściwości elektrycznych tkanki biologicznej.

2

Urukul : Open-source Frequency Synthesizer Module for Quantum Physics

Kasprowicz Grzegorz, Harty Thomas, Bourdeauducq Sébastien, Jördens Robert, Allcock David, Nadlinger David, Britton Joseph W., Sotirova Ana, Nowicka Dorota

International Journal of Electronics and Telecommunications

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2022

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Vol. 68, No. 1

123--128

EN

We describe Urukul, a frequency synthesizer based on direct digital synthesis (DDS), optimized for wave generate control in atomic, molecular and optical (AMO) physics experiments. The Urukul module is a part of the Sinara family of modular, open-source hardware designed for the ARTIQ quantum operating system. The Urukul has 4-channel, sub-Hz frequency resolution, controlled phase steps and accurate output amplitude control. The module is available in two population variants. This paper presents Urukul module construction and obtained characteristics.

3

Sampler: Open-Source Data Acquisition Module for Quantum Physics

Kasprowicz Grzegorz, Harty Thomas, Bourdeauducq Sébastien, Jördens Robert, Allcock David, Slichter Daniel, Nadlinger David, Britton Joseph W., Sotirova Ana

International Journal of Electronics and Telecommunications

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2022

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Vol. 68. No. 4

761--766

EN

The Sinara hardware platform is a modular, opensource measurement and control system dedicated to quantum applications that require hard real-time performance. The hardware is controlled and managed by the ARTIQ, open-source software that provides nanosecond timing resolution and submicrosecond latency. The Sampler is a general-purpose precision ADC sampling unit with programmable gain and configurable interface. It is used in numerous applications like laser frequency and intensity servo. This paper presents the Sampler module construction and obtained characteristics.

4

Analysis of a novel FPGA-based system for filtering audio signals using a finite impulse response filters

Lipowski Adrian, Majewski Paweł, Pluta Sławomir

International Journal of Electronics and Telecommunications

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2022

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Vol. 68, No. 1

19--26

EN

In this article, an analysis of an innovative system for filtering signals in the audible range (16 Hz - 20 kHz) on programmable logic devices using a filters with a finite impulse response, is presented. Mentioned system was neat combination of software and hardware platform, where in the program layer a multiple programming languages including VHDL, JavaScript, Matlab or HTML were used to create completely useful application. To determine the coefficients of polynomial filters the Matlab Filter Design & Analysis Tool was used. Thanks to the developed graphic layer, a user-friendly interface was created, which allows easily transfer the required coefficients from the computer to the executive system. The practical implementation made on the FPGA platform, specifically on the Altera DE2- 115 development kit with the FPGA Cyclone IV, was compared with simulation realization of Matlab FIR filters. The performed research confirm the effectiveness of filtration in real time with up to 128th order of the filter for both audio channels simultaneously in FPGA-based system.

5

An Efficient Classification of Hyperspectral Remotely Sensed Data Using Support Vector Machine

Mahendra H. N., Mallikarjunaswamy S.

International Journal of Electronics and Telecommunications

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2022

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Vol. 68. No. 3

609--617

EN

This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.

6

Improving the LUT count for Mealy FSMs with transformation of output collections

Barkalov Alexander, Titarenko Larysa, Mazurkiewicz Małgorzata

International Journal of Applied Mathematics and Computer Science

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2022

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Vol. 32, no. 3

479--494

EN

A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments were conducted using standard benchmarks. They show that the proposed method produces FSM circuits with significantly smaller LUT counts compared with those produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of output collection codes into extended state codes). The LUT count is decreased by, on average, from 9.86% to 59.64%. The improvement of the LUT count is accompanied by a slightly improved performance. The maximum operating frequency is increased, on average, from 2.74% to 12.93%. The advantages of the proposed method become more pronounced with increasing values of FSM inputs and state variables.

7

Sprzętowa akceleracja algorytmu przesiewania kraty

Andrzejczak Michał, Paszkiewicz Andrzej

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

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2021

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nr 1

20--26

PL

W artykule podjęto próby akceleracji sprzętowej algorytmu przesiewania kraty – algorytmu Gaussa, wykorzystywanego do rozwiązania problemu najkrótszego wektora w kracie algebraicznej. Użyty algorytm cechuje wykładnicza złożoność pamięciowa. Jest to główna przeszkoda na drodze do efektywnej akceleracji sprzętowej ze względu na ograniczoną dostępność pamięci w układach programowalnych oraz kosztowny czasowo transfer danych pomiędzy układami FPGA a magazynem danych. Rozwiązano problem ograniczonej pamięci oraz spowalniającej transmisji danych przez odpowiednie zmiany w konstrukcji algorytmu, wyspecjalizowaną architekturę akceleratora sprzętowego oraz zastosowanie technik buforowania danych, co zapewniło uzyskanie znacznego przyspieszenia dla wykorzystanego algorytmu.

EN

In this paper we try to accelerate lattice sieving with FPGAs to solve Shortest Vector Problem. Used algorithm has exponential memory requirements and this is the main bottleneck in efficient hardware implementation, due to memory size limitations and communication bandwidth between FPGA and storage. We solve these problems with appropriate changes in algorithm and specialized hardware architecture adopting caching techniques, which lead to achieve significant speed-up for chosen algorithm.

8

Algorytmy minimalizacji błędu bąbelkowego w precyzyjnej metrologii odcinka czasu

Gurski Maciej, Frankowski Robert, Zieliński Marek

Przegląd Elektrotechniczny

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2021

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R. 97, nr 10

100--102

PL

Referat dotyczy zagadnień związanych z konstrukcją wysokorozdzielczych systemów przeznaczonych do precyzyjnego pomiaru odcinka czasu implementowanych w strukturach programowalnych FPGA. Zawarto w nim najistotniejsze informacje na temat zastosowanych algorytmów sortowania segmentów linii wymaganych do uzyskania systemów o większej liniowości i rozdzielczości czasowej. Zaproponowane podejście umożliwia skuteczną minimalizację wpływu błędu bąbelkowego na proces przetwarzania.

EN

The paper describes issues related to the design of high-resolution time-interval measuring systems implemented in FPGA programmable structures. It contains the most important information on the applied of the line's segment sorting algorithms required to obtain systems with higher time resolution and linearity. The proposed approach makes it possible to effectively minimize the impact of bubble error on the conversion process. The presented solution is important from the perspective of designing high-resolution TDCs operating with multiplied delay lines.

9

Sprzętowa implementacja transformacji Hougha w czasie rzeczywistym

Kowalski Paweł, Smyka Robert

Poznan University of Technology Academic Journals. Electrical Engineering

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2021

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No. 106

45--55

PL

W artykule przedstawiono implementację sprzętową w FPGA algorytmu do wykrywania kształtów aproksymowanych zbiorem linii prostych podczas przetwarzania obrazu cyfrowego w czasie rzeczywistym. W opracowanej strukturze sprzętowej podniesiono efektywność przetwarzania poprzez zastosowanie przetwarzania przepływowego, lookup table, wykorzystanie wyłącznie arytmetyki liczb całkowitych oraz rozproszenie pamięci głosowania. Eksperymentalnie wykorzystano przedstawioną strukturę w torze przetwarzania obrazu w czasie rzeczywistym złożonym z kamery OV7670, płyty deweloperskiej Terasic DE10-nano oraz monitora podłączonego za pomocą HDMI. Pełny tor przetwarzania został zaimplementowany w pojedynczym układzie FPGA Intel Cyclone V. Maksymalna prędkość przetwarzania obrazu z wykorzystaniem opracowanej implementacji została określona na 275 MHz.

EN

The article presents the hardware implementation in FPGA of the algorithm for detecting shapes approximated by a set of straight lines. In the developed hardware structure, the efficiency of processing was increased through the use of pipeline processing, lookup table, using only integer arithmetic and distributed memory. The presented structure was used experimentally in the real-time image processing circuit consisting of the OV7670 camera, Terasic DE10-nano development board and a monitor connected via HDMI. The full processing path has been implemented in a single Intel Cyclone V FPGA chip. The maximum speed of image processing with the use of the developed implementation is 275 MHz.

10

Przegląd metod szybkiego prototypowania algorytmów uczenia maszynowego w FPGA

Smyk Robert, Kowalski Paweł

Poznan University of Technology Academic Journals. Electrical Engineering

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2021

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No. 106

31--43

PL

W artykule opisano możliwe do wykorzystania otwarte narzędzia wspomagające szybkie prototypowanie algorytmów uczenia maszynowego (ML) i sztucznej inteligencji (AI) przy użyciu współczesnych platform FPGA. Przedstawiono przykład szybkiej ścieżki przy realizacji toru wideo wraz z implementacją przykładowego algorytmu przetwarzania w trybie na żywo.

EN

The paper discusses open tools that can be used to support rapid prototyping of machine learning (ML) and artificial intelligence (AI) algorithms using contemporary FPGA platforms. An example of a fast path in the implementation of a video processing system was presented along with the implementation of an exemplary processing algorithm in live mode.

11

Development of Low-Resolution, Low-Power and Low-Cost Infrared System

Urbaś Sebastian, Więcek Bogusław

Pomiary Automatyka Robotyka

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2021

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R. 25, nr 2

47--52

EN

The article presents the construction of a thermal imaging camera with low power consumption. The 80 × 80 Micro80Gen2 microbolometric array of detectors records infrared radiation in the LWIR spectral range (long infrared wave, 8-12 μm). The entire digital part of the electronic circuit has been integrated within the reprogrammable FPGA chip from the Spartan 6 family. In order to read and display thermograms, an application for the .NetFremework 3.1 platform, which implements non-uniformity correction (NUC) and image processing, is written. Due to its low cost, small size and weight, the camera can be used in various applications, e.g. in unmanned aerial vehicles (UAV) known as drones.

PL

W artykule przedstawiono budowę i oprogramowanie kamery termowizyjnej μIR80 o niskim poborze mocy. Kamera wyposażona została w mikrobolometryczny detektor podczerwieni 80 × 80 - Micro80Gen2, który pochłania promieniowanie podczerwone w długofalowym zakresie spektralnym LWIR (8-12 μm). Cyfrowa część układu została zintegrowana w układzie FPGA z rodziny Spartan 6. W celu odczytu i wyświetlenia obrazu termalnego, napisane zostało oprogramowanie na platformie .NetFramework 3.1. Dodatkowo zaimplementowano 1-punktową korekcję niejednorodności matrycy detektora (NUC) oraz podstawowe algorytmy przetwarzania obrazów, np. wyznaczanie histogramu, zmianę zakresu i interpolację bikubiczną. Ze względu na niski koszt oraz niewielkie wymiary i masę, przedstawiona kamera termowizyjna może znaleźć zastosowanie w wielu dziedzinach począwszy od monitorowania otoczenia przy pomocy bezzałogowego statku powietrznego (UAV), po zastosowania w przemyśle, energetyce i medycynie.

12

Hardware rough set processor parallel architecture in FPGA for finding core in big datasets

Kopczyński Maciej, Grześ Tomasz

Journal of Artificial Intelligence and Soft Computing Research

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2021

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Vol. 11, No. 2

99--110

EN

This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this paper have been tested on two real datasets running presented solutions inside FPGA unit. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.

13

Hardware implementation of a Takagi-Sugeno neuro-fuzzy system optimized by a population algorithm

Dziwiński Piotr, Przybył Andrzej, Trippner Paweł, Paszkowski Józef, Hayashi Yoichi

Journal of Artificial Intelligence and Soft Computing Research

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2021

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Vol. 11, No. 3

243--266

EN

Over the last several decades, neuro-fuzzy systems (NFS) have been widely analyzed and described in the literature because of their many advantages. They can model the uncertainty characteristic of human reasoning and the possibility of a universal approximation. These properties allow, for example, for the implementation of nonlinear control and modeling systems of better quality than would be possible with the use of classical methods. However, according to the authors, the number of NFS applications deployed so far is not large enough. This is because the implementation of NFS on typical digital platforms, such as, for example, microcontrollers, has not led to sufficiently high performance. On the other hand, the world literature describes many cases of NFS hardware implementation in programmable gate arrays (FPGAs) offering sufficiently high performance. Unfortunately, the complexity and cost of such systems were so high that the solutions were not very successful. This paper proposes a method of the hardware implementation of MRBF-TS systems. Such systems are created by modifying a subclass of Takagi-Sugeno (TS) fuzzy-neural structures, i.e. the NFS group functionally equivalent to networks with radial basis functions (RBF). The structure of the MRBF-TS is designed to be well suited to the implementation on an FPGA. Thanks to this, it is possible to obtain both very high computing efficiency and high accuracy with relatively low consumption of hardware resources. This paper describes both, the method of implementing MRBFTS type structures on the FPGA and the method of designing such structures based on the population algorithm. The described solution allows for the implementation of control or modeling systems, the implementation of which was impossible so far due to technical or economic reasons.

14

Zero-Suppression Trigger Mode for GEM Detector Measurement System

Kolasinski Piotr, Pozniak Krzysztof, Wojenski Andrzej, Linczuk Pawel, Krawczyk Rafal, Gaska Michal, Zabolotny Wojciech, Kasprowicz Grzegorz, Chernyshova Maryna, Czarski Tomasz

International Journal of Electronics and Telecommunications

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2021

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Vol. 67, No. 1

103--108

EN

A novel approach to a trigger mode in the Gas Electron Multiplier (GEM) detector readout system is presented. The system is already installed at WEST tokamak. The article briefly describes the architecture of the GEM detector and the measurement system. Currently the system can work in two trigger modes: Global Trigger and Local Trigger. All trigger processing blocks are parts of the Charge Signal Sequencer module which is responsible for transferring data to the PC. Therefore, the article presents structure of the Sequencer with details about basic blocks, theirs functionality and output data configuration. The Sequencer with the trigger algorithms is implemented in an FPGA chip from Xilinx. Global Trigger, which is a default mode for the system, is not efficient and has limitations due to storing much data without any information. Local trigger which is under tests, removes data redundancy and is constructed to send only valid data, but the rest of the software, especially on the PC side, is still under development. Therefore authors propose the trigger mode which combines functionality of two existing modes. The proposed trigger, called Zero Suppression Trigger, is compatible with the existing interfaces of the PC software, but is also capable to verify and filter incoming signals and transfer only recognized events. The results of the implementation and simulation are presented.

15

SoPC-based DMA for PCI Express DAQ cards

Mroczek Krzysztof

International Journal of Electronics and Telecommunications

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2021

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Vol. 67, No. 4

565--570

EN

This paper presents low-cost, configurable PCI Express (PCIe) direct memory access (DMA) interface for implementation on Intel Cyclone V FPGAs. The DMA engine was designed to support DAQ tasks including pre-triggering acquisition for transient analysis and multichannel transmission. Performance of the interface has been evaluated on Terasic OVSK board (PCIe Gen2 x4). Target configuration of this interface is based on the Avalon-MM Hard IP for Cyclone V PCIe core and Jungo WinDriver x64 for Windows. A sample speed of 1200 MB/s has been reported for DMA writes to PCIe memory.

16

Soft X-ray Diagnostic System Upgrades and Data Quality Monitoring Features for Tokamak Usage

Wojenski Andrzej, Linczuk Paweł, Piotr Kolasinski, Chernyshova Maryna, Mazon Didier, Kasprowicz Grzegorz, Pozniak Krzysztof T., Gaska Michał, Czarski Tomasz, Krawczyk Rafał

International Journal of Electronics and Telecommunications

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2021

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Vol. 67, No. 1

109--114

EN

The validation of the measurements quality after on-site diagnostic system installation is necessary in order to provide reliable data and output results. This topic is often neglected or not discussed in detail regarding measurement systems. In the paper recently installed system for soft X-ray measurements is described in introduction. The system is based on multichannel GEM detector and the data is collected and sent in special format to PC unit for further postprocessing. The unique feature of the system is the ability to compute final data based on raw data only. The raw data is selected upon algorithms by FPGA units. The FPGAs are connected to the analog frontend of the system and able to register all of the signals and collect the useful data. The interface used for data streaming is PCIe Gen2 x4 for each FPGA, therefore high throughput of the system is ensured. The paper then discusses the properties of the installation environment of the system and basic functionality mode. New features are described, both in theoretical and practical approach. New modes correspond to the data quality monitoring features implemented for the system, that provide extra information to the postprocessing stage and final algorithms. In the article is described also additional mode to perform hardware simulation of signals in a tokamak-like environment using FPGAs. The summary describes the implemented features of the data quality monitoring features and additional modes of the system.

17

FID-MA XTEA : Cost-Effective RFID-Mutual Authentication Design Using XTEA Security on FPGA Platform

Anusha R., Shastrimath V. Veena Devi

International Journal of Electronics and Telecommunications

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2021

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Vol. 67, No. 4

623--629

EN

RFID systems are one of the essential technologies and used many diverse applications. The security and privacy are the primary concern in RFID systems which are overcome by using suitable authentication protocols. In this manuscript, the cost-effective RFID-Mutual Authentication (MA) using a lightweight Extended Tiny encryption algorithm (XTEA) is designed to overcome the security and privacy issues on Hardware Platform. The proposed design provides two levels of security, which includes secured Tag identification and mutual authentication. The RFID-MA mainly has Reader and Tag along with the backend Server. It establishes the secured authentication between Tag and Reader using XTEA. The XTEA with Cipher block chaining (CBC) is incorporated in RFID for secured MA purposes. The authentication process completed based on the challenge and response between Reader and Tag using XTEA-CBC. The present work is designed using Verilog-HDL on the Xilinx environment and implemented on Artix-7 FPGA. The simulation and synthesis results discussed with hardware constraints like Area, power, and time. The present work is compared with existing similar approaches with hardware constraints improvements.

18

Improving LUT count of FPGA-based sequential blocks

Barkalov Alexander, Titarenko Larysa, Mazurkiewicz Małgorzata, Krzywicki Kazimierz

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2021

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Vol. 69, nr 2

art. no. e136728

EN

Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.

19

FPGA based real-time epileptic seizure prediction system

Cosgun Ercan, Çelebi Anil

Biocybernetics and Biomedical Engineering

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2021

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Vol. 41, no. 1

278--292

EN

The development of systems that can predict epileptic seizures in real-time offers great hope for epilepsy patients. These systems aim to prevent accidents that patients may experience caused by the loss of consciousness during seizures. Therefore, patients must use real-time epileptic seizure prediction systems that do not interfere with their daily activities. In this study, using the unipolar EEG data from a surface electrode, a patient-specific estimation system is implemented in real-time on a system on chip (SoC) that contains an embedded processor and programmable logic blocks. The European epilepsy database EPILEPSIAE is used in the scope of this work. In the proposed system, pre-processing is applied to the EEG data. Then, the features of the data in the frequency domain are extracted. The classifier model is trained with the RusBoosted Tree cluster classifier, which is a machine learning algorithm. Testing is carried out using the proposed classification model. Threshold values are determined, and then false alarms and erroneous classifications are prevented by post-processing. At the end of the tests, prediction success, sensitivity (SEN), Specificity (SPE), False Prediction Rate (FPR), and prediction times are obtained as 77.30%, 95.94%, 0.041 h_1, and 33.23 min, respectively. The proposed system outperforms other studies in the liter-ature in the number of electrodes, real-time operation, hardware/software architecture, and FPR performance. A wearable seizure prediction system seems to be commercialized according to the results achieved in this study.

20

Układy FPGA jako sprzętowy analizator stanów pól komutacyjnych typu multi-log2N

Michalski Marek

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

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2020

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nr 7-8

246--249, CD

PL

Niniejszy artykuł prezentuje system do symulacji i analizy stanu pól komutacyjnych. Główną cechą systemu jest to, że obliczenia saą realizowane w dedykowanych układach sprzętowych. Jako moduły obliczeniowe wykorzystane zostały moduł z programowalnym układem FPGA -Spartan-3 firmy Xilinx. Kilkanaście takich modułów zostało połączonych w szeregowy systemi pracuą˛pod kontrolą aplikacji www, która komunikuje się z węzłami obliczeniowymi za pośrednictwem Raspberry Pi, który to realizuje funkcjonalność proxy między typowym oprogramowaniem a programowalnymi układami sprzętowymi.

EN

In this paper there is presented a system for simulations realized in hardware. The subject are blocking states in optical switching fabrics. Model of such a fabric is presented, and the way of its analysis is described. FPGA Spartan-3 chips are used for fast calculations, Raspberry PI, small PC, is used as an interface between PC and electronic part of the system. System is dedicated for searching blocking states (which is realized in hardware) and their analysis (which is realized by GUI and software on PC). Main elements of system are:Web based GUI, scripts and database for storing results, subsystem for controlling FPGA chips (controller is realized on Raspberry PI and its GPIOs) and 18 (or more) FPGA modules as a calculating engines.