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http://yadda.icm.edu.pl:80/baztech/element/bwmeta1.element.baztech-efcf060a-e5b7-4ece-bc85-c8996ddd4827

Czasopismo

Opto - Electronics Review

Tytuł artykułu

Automation of CMOS technology migration illustrated by RGB to YCrCb analogue converter

Autorzy Naumowicz, M.  Melosik, M.  Katarzynski, P.  Hankiewicz, A. 
Treść / Zawartość http://www.wat.edu.pl/review/optor/contents.htm
Warianty tytułu
Języki publikacji EN
Abstrakty
EN The paper illustrates a practical example of technology migration applied to the colour space converter realized in CMOS technology. The element has analogue excitation and response signals expressed in current mode. Such converter may be incorporated into an integrated vision sensor for preconditioning acquired image data. The idea of a computer software tool supporting the automated migration and design reuse is presented as the major contribution. The mentioned tools implement the Hooke-Jeeves direct search method for performing the multivariable optimization. Our purpose is to ensure transferring the circuit between usable fabrication technologies and preserving its functional properties. The colour space converter is treated as the case study for performance evaluation of the proposed tool in cooperation with HSPICE simulation software. The original CMOS technology files for Taiwan semiconductor (TSMC) plant were utilized for the research. The automated design migration from 180 nm into 90 nm resulted with obtaining compact IC layout characterized by a smaller area and lower power consumption. The paper is concluded with a brief summary that proves the usability of the proposed tool in designing CMOS cells dedicated for low power image processing.
Słowa kluczowe
EN technology migration   colour space converter   YCrCb   RGB   TSMC   nanoscale CMOS   current mode   Hooke-Jeeves  
Wydawca Wojskowa Akademia Techniczna im. Jarosława Dąbrowskiego
Czasopismo Opto - Electronics Review
Rocznik 2013
Tom Vol. 21, No. 3
Strony 326--331
Opis fizyczny Bibliogr. 19 poz., rys., tab.
Twórcy
autor Naumowicz, M.
autor Melosik, M.
  • Chair of Computer Engineering, Poznan University of Technology, 5 M. Skłodowskiej-Curie Sq., 60-965 Poznan, Poland
autor Katarzynski, P.
  • Chair of Computer Engineering, Poznan University of Technology, 5 M. Skłodowskiej-Curie Sq., 60-965 Poznan, Poland
autor Hankiewicz, A.
  • Chair of Computer Engineering, Poznan University of Technology, 5 M. Skłodowskiej-Curie Sq., 60-965 Poznan, Poland
Bibliografia
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2. T. Levi, T. J. Lewis, et al., “A CMOS resizing methodology for analogue circuits”, IEEE Des. Test Compu. 26, 78-87 (2009).
3. K. Francken and G. Gielen, “Methodology for analogue technology porting including performance tuning”, Proc. IEEE Int. Conf. on Circuits and Systems, pp. 415-418, Orlando, 1999.
4. A. F. B. Adnan, A. K. B Aain, M. N. B. Marsono, I. B. Kamisan, and I. A. Grout, “Second-stage tuning procedure for analogue CMOS design reuse methodology”, Electron. Lett. 48, 990-992 (2012).
5. T. Yang, M. Gao, S. Wu, and D. Guo, “A new reuse method of analogue circuit design for CMOS technology migration”, Int. Conf. on Anti-Counterfeiting Security and Identification in Communication, pp. 112-115 (2010).
6. A. Handkiewicz, Mixed-Signal Systems, A Guide to CMOS Circuit Design, edited by John Wiley & Sons INC, New York, 2002.
7. K. Kimo and P. In-Cheol, “Combined image signal processing for CMOS image sensors”, IEEE Symp.on Circuits and Systems., pp. 3185-3188, Island of Kos, 2006.
8. E. Vittoz, “Analogue VLSI signal processing: Why, where and how”, Analog Integr. Circ. S. 6, 27-44 (1994).
9. B. Ahirwal, M. Khadtare, and R. Mehta, “FPGA based system for colour space transformation RGB to YIQ and YCbCr”, Proc. Int. Conf. on Intelligent and Advanced Systems, pp. 1345-1349, Kuala Lumpur, 2007.
10. S-A. Li, C-Y. Chen, C-H Chen,” Design of a shift-and-add based hardware accelerator for colour space conversion”, J. Real-Time Image Proc., http://dx.doi.org/10.1007/ s11554-013-0324-7 (1999).
11. M. Goroń, “Parallel performance of the fine-grain pipeline FPGA image processing system”, Opto−Electron. Rev., 20, 153-158 (2012).
12. A. Handkiewicz, P. Sniatala, G. Palaszynski, S. Szczesny, P. Katarzynski, M. Melosik, M. Naumowicz, “Automatem DCTgeneration using ample language”, Proc. Int. Conf. on Mixed Design of Integrated Circuits and Systems, pp. 215-218, Warsaw, (2010).
13. A. Handkiewicz, Sz. Szczesny , M. Naumowicz, M. Melosik, P. Katarzynski „Generacja layoutu filtrow SI w strategii wierszowej”, Przegląd Elektrotechniczny, 10, 80-83 (2011). (IN POLISH).
14. S. Szczęsny, M. Naumowicz, A. Handkiewicz, “SI-Studio - environment for SI circuits design automation”, Bull Pol. Acad. Sci-Te. Vol. 60, pp. 757-762 (2013).
15. R. Hooke and T. A. Jeeves, “Direct search solution of numerical and statistical problems”, J. Association for Comput. Machinery 8, 212-229 (1961).
16. M. Melosik and M. Naumowicz, “Implementation and comparison for methods of solving non-linear algebraic equations in design of lossless prototype circuits”, Engineering Thesis, 2008.
17. L. L. Lewyn, T. Ytterdal, C. Wulff, and K. Martin, “Analogue circuit design in nanoscale cmos technologies”, Proc. IEEE 97, 1687-1714, (2009).
18. J. Puhan, T. Tuma, and I. Fajfar, “Optimisation methods in spice, a comparison”, Proc. Eur. Conf. on Circuit Theory and Design 2, 1279-1282 (1999).
19. L. Tutelea and I. Boldea, “Induction motor electromagnetic design optimization: Hooke Jeeves method versus genetic algorithms”, Proc. Int. Conf. on Optimization of Electrical and Electronic Equipment, 485-492 (2010).
Kolekcja BazTech
Identyfikator YADDA bwmeta1.element.baztech-efcf060a-e5b7-4ece-bc85-c8996ddd4827
Identyfikatory
DOI 10.2478/s11772-013-0097-3