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MPS(3N) transparent memory test for Pattern Sensitive Fault detection

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Języki publikacji
EN
Abstrakty
EN
Conventional memory tests based on only one run have constant and low faults coverage especially for Pattern Sensitive Faults (PSF). To increase faults coverage the multiple run March test algorithms have been used. As have been shown earlier the key element of multiple run March test algorithms are memory backgrounds. Only in a case of optimal set of backgrounds the high fault coverage can be achieved. For such optimal backgrounds the analytical calculation of NPSFk fault coverage for 3 and 4 runs of MPS(3N) test in this paper is presented. All of the analytical calculations are confirmed and validated by adequate experiments.
Rocznik
Strony
129--138
Opis fizyczny
Bibliogr. 11 poz., rys., tab.
Twórcy
autor
  • Bialystok Technical University, Faculty of Computer Science
  • Bialystok Technical University, Faculty of Computer Science
autor
  • Bialystok Technical University, Faculty of Computer Science
Bibliografia
  • [1] Goor A. J. V. D. Testing Semiconductor Memories: Theory and Practice. Chichester, England: John Wiley & Sons, 1991.
  • [2] Hayes J. P. Detection of pattern-sensitive faults in random-access memories. IEEE Trans. Computers, vol. 24, no. 2, pp. 150–157, 1975.
  • [3] Cockburn B. F. Deterministic tests for detecting scrambled pattern sensitive faults in RAMs, in MTDT ’95: Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing. Washington, DC, USA: IEEE Computer Society, pp. 117–122, 1995.
  • [4] Franklin M., Saluja K. K. Testing reconfigured RAM’s and scrambled address RAM’s for pattern sensitive faults, IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 15, no. 9, pp. 1081–1087, 1996.
  • [5] Karpovsky M. G., Yarmolik V. N. Transparent memory testing for patternsensitive faults, in Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years. Washington, DC, USA: IEEE Computer Society, pp. 860–869, 1994.
  • [6] Nicolaidis M. Theory of transparent BIST for RAMs, IEEE Trans. Comput., vol. 45, no. 10, pp. 1141–1156, 1996.
  • [7] Yarmolik V. N., Klimets Y., Demidenko S. March PS(23N) test for DRAM patternsensitive faults, in ATS ’98: Proceedings of the 7th Asian Test Symposium. Washington, DC, USA: IEEE Computer Society, pp. 354–357, 1998.
  • [8] Yarmolik V. N. Contents independent RAM built in self test and diagnoses based on symmetric transparent algorithm, in DDECS’2000: Proceedings of the 3rd Workshop on Design and Diagnostics of Electronic Circuits and Systems, Smolenice - Slovakia, April 5-7, pp. 220–227, 2000.
  • [9] Yarmolik V. N., Murashko I., Kummert A., Ivaniuk A. Transparent Testing of Digital Memories, Minsk, Belarus: Bestprint, 2005.
  • [10] Yarmolik S. V. Address sequences with different average hamming distance, in: Abstracts of 1st International Conference for Young Researches in Computer Science, Control Electrical Engineering and Telecommunications, Zielona Gora, Poland, September 18-20, pp. 67–68, 2006.
  • [11] Yarmolik S. V., Mrozek I. Multi background memory testing, in MIXDES2007: Proceedings of the 14th International Conference Mixed design of integrated circuits and systems. Ciechocinek, Poland: IEEE Computer Society, June 21-23, pp. 511–516, 2007.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-d332c93a-3f53-428c-8f5b-bb70d2dd3e56
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