Tytuł artykułu
Autorzy
Wybrane pełne teksty z tego czasopisma
Identyfikatory
Warianty tytułu
Konferencja
Fifth Symposjum on Image Processing Technology (TPO 2006) ; (5 ; 21-23.11.2006 ; Serock, Poland)
Języki publikacji
Abstrakty
Reconfigurable computers are becoming third, after general purpose processors and digital signal processors, programmable computing systems. In the present paper, a new definition of parallelism adequate for fine-grain parallel systems is introduced. Computing power requirements for high definition, real-time vision system are discussed. A survey of reconfigurable solutions for image processing and the latest research work carried on at the AGH Laboratory of Biocybernetics are presented.
Wydawca
Czasopismo
Rocznik
Tom
Strony
196--201
Opis fizyczny
Bibliogr. 42 poz., tab., wykr.
Twórcy
autor
- Institute of Automatics, University of Science and Technology, Al. Mickiewicza 30, 30-059 Cracow, mago@agh.edu.pl
Bibliografia
- 1. G. Estrin, "Organization of computer systems - the fixed plus variable structure computer", Proc. Western Joint Computer Conf., New York, 33-40 (1960).
- 2. R. Hartenstein, "Reconfigurable computing: A new business model - and its impact on SoC design", Proc. Euromicro Symp. on Digital System Design, Los Alamos, 103-110(2001).
- 3. C. Chang, J. Wawrzynek, and R.W. Broadersen, "A high-end reconfigurable computing system", IEEE Design & Test of Computers 22, 85-89 (2005).
- 4. J.L. Tripp, H.S. Mortveit, A.A. Hansson, and M. Gokhale, "Metropolitan road traffic simulation on FPGAs", Proc. 13th Annual IEEE Symp. on Field-Programmable Custom Computing Machines, Los Alamitos, 117-126 (2005).
- 5. K. Wiatr, Acceleration of Calculations in Vision Systems, WNT, Warsaw, 2003. (in Polish).
- 6. L.R. Scott, T. Clark, and B. Bagheri, Scientific Parallel Computing, Princeston University Press, Princeston, 2005.
- 7. M. Gorgoń, S. Cichoń, and M. Pac, "Real-time handel-C based implementation of DV decoder", Proc. Int. Conf. On Field Programmable Logic and Applications, New York, 130-135 (2005).
- 8. S. McBader and P. Lee, "An FPGA implementation of a flexible, parallel image processing architecture suitable for embedded vision systems", Int. Parallel and Distributed Processing Symp., Los Alamitos, 228 (2003).
- 9. A. Amira, A. Bouridane, P. Milligan, and F. Bensaali, "Custom coprocessor based matrix algorithms for image and signal processing", Lecture Notes in Computer Science 2438, pp. 731-739, Springer-Verlag, Berlin, 2002.
- 10. S. Cuenca-Asensi, I.F. Pico, and R. Alvarez, "Reconfigurable frame-grabber for real-time automated visual inspection (RT-AVI)", Lecture Notes in Computer Science 2147, pp. 223-231, Springer, Heilderberg, 2001.
- 11. W.J.C. Melis, P.Y.K. Cheung, and W. Luk, "Image registration of real-time broadcast video using the UltraSONIC reconfigurable computer", Lecture Notes in Computer Science 2438, Springer- Verlag, Berlin, 2002.
- 12. M. Gorgoń and R. Tadeusiewicz, "Hardware-based image processing library for Virtex FPGA", Proc. SPIE 4212, 1-10 (2000).
- 13. F.I. Pico, S. Cuenca-Asensi, and V. Corcoles, "Accelerating statistical texture analysis with an FPGA-DSP hybrid architecture", Proc. 9th Annual IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 289-290, Los Alamitos, 2001.
- 14. M. Gorgoń and M. Jabłoński, "FPGA-based video processor for log-polar re-mapping in the retina heterogenous image processing system", Programmable Devices and Systems 2001, Proc. 5th IF AC Workshop, 49-54 (2002).
- 15. E. Garcia, "Implementing a histogram for image processing application", Xcell Journal 38, 46-47 (2000).
- 16. E. Jamro and K. Wiatr, "Dynamic constant coefficient convolvers implemented in FPGAs", Lecture Notes in Computer Science 2438, pp. 1110-1113, Springer-Verlag, Berlin, 2002.
- 17. L. Jianchun, C. Papachristou, and R. Shekhar, "A reconfiurable SoC architecture and caching scheme for 3D medical image processing", Proc. 12th Annual IEEE Symp. On Field-Programmable Custom Computing Machines, pp. 30-321, Los Alamitos, 2004.
- 18. The Programmable Logic Data Book 2000, Xilinx, Inc, San Jose.
- 19. A. Pelkonen, K. Masselos, and M. Cupak, "System-level modelling of dynamically reconfigurable hardware with SystemC", Proc. Int. Symp. on Parallel and Distributed Proc, 174b, Los Alamitos, 2003.
- 20. X. Weifeng, R. Ramshankar, and T. Russell, "Runtime assignment of reconfigurable hardware components for image processing pipelines", Proc. the 11th Annual IEEE Symp. On Field-Programmable Custom Computing Machines, pp. 173-183, Los Alamitos, 2003.
- 21. M.R. Boschetti, S. Bampi, and I.S. Silva, "Throughput and reconfiguration time trade-offs: From static to dynamic reconfiguration in dedicated image filters", Lecture Notes in Computer Science 3203, pp. 474-483, Springer Berlin, 2004.
- 22. T. Rissa, P.Y.K. Cheung, and W. Luk, "SoftSONIC: A customisable modular platform for video applications", Lecture Notes in Computer Science 3203, pp. 54-63, Springer, Berlin, 2004.
- 23. T. Yokota, M. Nagafuchi, Y. Mekada, T. Yoshinaga, K. Ootsu, and T. Baba, "A scalable FPGA-based custom computing machine for a medical image processing", Proc. 10th Annual IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 3-12, Los Alamitos, 2002.
- 24. M.A. Tahir, A. Bouridane, and F. Kurugollu, "An FPGAbased coprocessor for the classification of tissue patterns in prostatic cancer", Lecture Notes in Computer Science 3203, pp. 771-780, Springer, Berlin, 2004.
- 25. C. López-Ongil, R. Sanchez-Reillo, J. Liu-Jiminez, L. Sanchez, and L. Entrena, "FPGA implementation of biometric authentication system based on hand geometry", Lecture Notes in Computer Science 3203, pp. 43-53, Springer, Berlin, 2004.
- 26. K. Benkrid, D. Crookes, J. Smith, and A. Benkrid, "High level programming for FPGA based image and video processing using hardware skeletons", Proc. 9th Annual IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 219-226, Los Alamitos, 2001.
- 27. K. Buchenrieder, U. Nageldinger, A. Pyttel, and A. Sedlmeier, "Integration of reconfigurable hardware into system-level design", Lecture Notes in Computer Science 2438, pp. 987-996, Springer-Verlag, Berlin, 2002.
- 28. S. Hemmert, B. Hutchings, and A. Malvi, "An application-specific compiler for high-speed binary image morphology", Proc. 9th Annual IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 199-208, Los Alamitos, 2001.
- 29. P. Voles, L. Holasek, and M. Vasilko, "ANSI C and handel-C based rapid prototyping framework for real-time image processing algorithms", Proc. Int. Conf. Engineering of Reconfigurable Systems and Algorithms, pp. 153-159, CRSEA Press, Las Vegas, (2002).
- 30. M. Gorgoń and M. Jabłoński, "Handel-C implementation of handwritten digits recognition", Programmable Devices and Systems, Proc. 6th IFAC Workshop, pp. 167-170, Elsevier Ltd., 2003.
- 31. T. Todman and W. Luk, "Methods and tools for high-resolution imaging", Lecture Notes in Computer Science 3203, pp. 627-636, Springer, Berlin, 2004.
- 32. M. Gorgoń, "Software-hardware environment for aquisition, processing, and visualisation of complex signals based on new generation FPGA systems", accepted for Automatyka AGH. (in Polish).
- 33. J. Diaz, E. Ros, S. Mota, and R. Rodriguez-Gomez, "Highly paralellized architecture for image motion estimation, reconfigurable computing: Architectures and applications", Lecture Notes in Computer Science 3985, pp. 75-86, Springer-Verlag, Berlin, 2006.
- 34. S. Mota, E. Ros, J. Daz, and F. de Toro, "General purpose real-time image segmentation system", Lecture Notes in Computer Science 3985, pp. 164-169, Springer-Verlag, Berlin, 2006.
- 35. M. Gorgoń and M. Wrzesiński, "Neural network implementation in reprogrammable FPGA devices - an example of MLP", Lecture Notes in Artificial Intelligence 4029, pp. 19-28, Springer- Verlag, Berlin, 2006.
- 36. S. Yang, W. Wolf, and N. Vijaykrishnan, "Power and performance analysis of motion estimation based on hardware and software realizations", IEEE Transactions on Computers 54, 714-726 (2005).
- 37. M. Aubury, "Bringing imaging to the system level with pixel streams", Xcell Journal 58, 12-15 (2006).
- 38. M. Gorgoń, P. Pawlik, J. Przybyło, and M. Jabłoński, "Modelling and implementation of videodetecting algorithms on the FPGA platform", Automatyka AGH, 355-364 (2006).
- 39. Celoxica, Platform Developer’s Kit, RC300 Manual, Celoxica Ltd, 2005.
- 40. M. Jabłoński, J. Przybyło, and M. Gorgoń, "Real-time implementation of motion detection algorithm based on pixelstreams", Proc. IFAC Workshop on Programmable Devices and Embedded Systems, IFAC, pp. 186-190, Brno, 2006.
- 41. A. Zawadzki, "Implementation of an algorithm of hand movement in Handel-C", Master Dissertation, E.A.I. and E. Department, AGH, 2006. (in Polish).
- 42. R. Olechowski and M. Nowak, "Configuration and cooperation of programmes of traffic analysis in Linux system", M.A. Thesis, E.A.I. and E. Department, AGH, Cracow, 2003.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA9-0012-0011