Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs
Treść / Zawartość
Distributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures.
Bibliogr. 11 poz.
- Institute of Telecommunications, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland, email@example.com
-  U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 2nd ed. Berlin: Springer-Verlag, 2004.
-  K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.
-  M. A. M. Eshtawie and M. Othman, “On-line DA-LUT architecture for high-speed high-order digital FIR filters,” in Proceedings of the IEEE International Conference on Communication Systems, Singapore, November 2006, p. 5.
-  P. K. Meher, “Hardware-efficient systolization of DA-based calculation of finite digital convolution of finite digital convolution,” IEEE Transactions on Circuit and Systems II: Express Briefs, vol. 53, no. 8, pp. 707-711, 2006.
-  J. Xie, J. Heand, and G.Tan, “FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures,” Microelectronics Journal, vol. 41, no. 6, pp. 365-370, 2010.
-  J. Cong and K. Yan, “Synthesis for FPGas with embedded memory blocks,” FPGA. New York, pp. 75-82, 2000.
-  S. Krishnamoorthy and R. Tessier, “Technology mapping algorithms for hybrid FPGAs containing lookup tables and plas,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 545-559, 2003.
-  M. Rawski, T. Łuba, Z. Jachna, and P. Tomaszewicz, “The influence of functional decomposition on modern digital design process,” Design of Embedded Control Systems, pp. 193-203, 2005.
-  T. Sasao, Y. Iguchi, and T. Suzuki, “On LUT cascade realizations of fir filters,” in Proceedings of Eighth Euromicro Conference on Digital System Design, Architectures, Methods and Tools, C. Wolinski, Ed., Porto, 2005, pp. 467-475.
-  M. Rawski, P. Tomaszewicz, H. Selvaraj, and T. Łuba, “Efficient implementation of digital filtres with use of advanced synthesis methods targeted FPGA architectures,” in Proceedings of Eighth Euromicro Conference on Digital System Design, Architectures, Methods and Tools, C. Wolinski, Ed., Porto, 2005, pp. 460-466.
-  P. Jamieson and J. Rose, “A verilog RTL synthesis tool for heterogeneous FPGAs,” in International Conference on Field Programmable Logic and Applications, 2005, pp. 305-310.