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The paper deals with the problem of checking reachability for timed automata. The main idea consists in combining the well-know forward reachability algorithm and the Bounded Model Checking (BMC) method. In order to check reachability of a state satisfying some desired property, first the transition relation of a timed automaton is unfolded to the depth k Î N and encoded as a prepositional formula. Next the desired property is translated to a prepositional formula and the satisfiability of the conjunction of the two above defined formulas is checked. The unfolding of the transition can be terminated when either a state satisfying the property has been found or all the states of the timed automaton have been searched. The efficiency of the method is strongly supported by the experimental results. Keywords : Reachability problem, bounded model checking, translation to SAT, Timed Automata, Augmented Region Graphs, discretization.
Testowanie osiągalności automatów czasowych z wykorzystaniem SAT. Praca opisuje nowe podejście do problemu osiągalności dla automatów czasowych. Główna idea polega na połączeniu znanego algorytmu przeszukującego przestrzeń stanów wszerz metodą BFS oraz metody ograniczonej weryfikacji modelowej. Aby sprawdzić, czy stan spełniający daną własność jest osiągalny w modelu dla rozważanego automatu czasowego postępujemy następująco. Rozwijamy stopniowo relację przejścia dla automatu, aż do głębokości k Î N i kodujemy ją jako formułę zdaniową. Następnie, za pomocą formuły zdaniowej kodowana jest rozważana własność i sprawdzana jest spełnialność koniunkcji obydwu zdefiniowanych formuł zdaniowych. Rozwijanie relacji przejścia może zostać zakończone jeśli poszukiwany stan został znaleziony lub wszystkie stany danego automatu czasowego zostały przeszukane.
Wydawca
Rocznik
Tom
Strony
1--19
Opis fizyczny
Bibliogr. 30 poz., rys.
Twórcy
autor
- Institute of Mathematics and Computer Science, PU, Armii Krajowej 13/15, 42-200 Częstochowa, Poland
autor
- Institute of Computer Science, PAS, Ordona 21, 01-237 Warsaw, Poland
autor
- Institute of Mathematics and Computer Science, PU Armii Krajowej 13/15, 42-200 Częstochowa, Poland
Bibliografia
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- [KLK96] I. Kang, I. Lee, and Y. S. Kim. A state minimization technique for Timed Automata. In Proc. of Int. Workshop on Verification of Infinite State Systems (INFINITY’96), August 1996.
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- [MMZ+01] M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Proc. of the 38th Design Automation Conference (DAC01), pages 530-535, June 2001.
- [NMA+02] P. Niebert, M. Mahfoudh, E. Asarin, M. Bozga, O. Maler, and N. Jain. Verification of Timed Automata via Satisfiability Checking. In Proc. of the 7th Int. Symp. on Formal Techniques in Real-Time and Fault Tolerant Systems (FTRTFT’02), volume 2469 of LNCS, pages 226-243. Springer-Verlag, 2002.
- [NTY00] P. Niebert, S. Tripakis, and S. Yovine. Minimum-time reachability for Timed Automata. In Proc. of the 8th IEEE Mediterranean Conf. on Control and Automation (MED’2000), Patros, Greece, July 2000. IEEE Comp. Soc. Press.
- [PWZ02a] W. Penczek, B. Woźna, and A. Zbrzezny. Bounded model checking for the universal fragment of CTL. Fundamenta Informaticae, 51 (1-2): 135—156, June 2002.
- [PWZ02b] W. Penczek, B. Woźna, and A. Zbrzezny. SAT-Based Bounded Model Checking for the Universal Fragment of TCTL. Technical Report 947, ICS PAS, Ordona 21, 01 - 237 Warsaw, September 2002.
- [PWZ02c] W. Penczek, B. Woźna, and A. Zbrzezny. Towards bounded model checking for the universal fragment of TCTL. In Proc. of the 7th Int. Symp. on Formal Techniques in Real-Time and Fault Tolerant Systems (FTRTFT’02), volume 2469 of LNCS, pages 265-288. Springer-Verlag, 2002.
- [SebOl] R. Sebastiani. Integrating SAT solvers with math reasoners: Foundations and basic algorithms. Technical Report 0111-22, ITC-IRST, Sommarive 16, 38050 Povo, Trento, Italy, November 2001.
- [Sor02] Maria Sorea. Bounded modePchecking for timed automata. In Proc. of the Third Workshop on Models for Time-Critical Systems (MTCS’02); affiliated with CONCUR 2002., volume 68(5) of Electronic Notes in Theoretical Computer Science. Elsevier Science Publishers, 2002.
- [SSS00] M. Sheeran, S. Singh, and G. Stalmarck. Checking safety properties using induction and a SAT-solver. In Proc. of the Int. Conf. on Formal Methods in Computer-Aided Design (FMCAD’00), volume 1954 of LNCS, pages 108-125. Springer-Verlag, 2000.
- [Tri98] S. Tripakis. Minimization of timed systems, http://verimag.imag.fr/~tripakis/dea.ps.gz, 1998.
- [Tri99] S. Tripakis. Timed diagnostic for reachability properties. In Proc. of TACAS’99, volume 1579 of LNCS, pages 59-73. Springer-Verlag, 1999.
- [TY01] S. Tripakis and S. Yovine. Analysis of timed systems using time-abstracting bisimulations. Formal Methods in System Design, 18(1):25—68, 2001.
- [Yov97] S. Yovine. Model checking Timed Automata. In Embedded Systems, volume 1494 of LNCS, pages 114-152. Springer-Verlag, 1997.
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