Narzędzia help

Preferencje help
Widoczny [Schowaj] Abstrakt
Liczba wyników
first previous next last
cannonical link button


Metrology and Measurement Systems

Tytuł artykułu

Fault diagnosis in analog electronic circuits - the SVM approach

Autorzy Grzechca, D.  Rutkowski, J. 
Treść / Zawartość
Warianty tytułu
Języki publikacji EN
EN In this paper, the application of the SVM (Support Vector Machine) algorithm has been used for diagnosis and tests of analog electronic circuits. The diagnosis procedure belongs to simulation-before-test techniques, where simulations of the circuit under test (CUT) are performed at the before-test stage. Two examples have been verified for parametric and catastrophic faults in the time domain, but the conclusion is driven with the use of assumed features. A fault-driven test (FDT) has been applied to a filter circuit and a specification-driven test (SDT) to a field-programmable analog array (FPAA). The SVM classifies features which are calculated from the time domain responses. Results obtained from the examples prove a high detection and localization level of circuit states with the use of the SVM classifier.
Słowa kluczowe
EN fault diagnosis   electronic circuits   support vector machine (SVM)  
Wydawca Komitet Metrologii i Aparatury Naukowej PAN
Czasopismo Metrology and Measurement Systems
Rocznik 2009
Tom Vol. 16, nr 4
Strony 583--597
Opis fizyczny Bibliogr. 29 poz., rys., tab., wykr.
autor Grzechca, D.
autor Rutkowski, J.
  • Silesian University of Technology, Institute of Electronics, Division of Circuit and Signal Theory, Akademicka 16, 44-100 Gliwice, Poland,
[1] L.S. Milor: “A Tutorial Introduction t o Research on Analog and Mixed-Signal Circuit Testing.” IEEE Trans. on Circuits and Systems-II, vol. 45, no. 10, 1998, pp. 1389-1407.
[2] I.L. Huertas: “Test and design for testability of analog and mixed-signal integrated circuits: theoretical basis and pragmatical approaches.” Proc. ECCTD Conf., 1993, pp. 75-156.
[3] L. Bushnell, Vishwani D. Agrawal: “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”. Kluwer Academic Publishers, 2002, ISBN: 0-306-47040-3.
[4] P.M. Lin, Y.S. Elcherif: Computational Approaches to Fault Dictionary, Analog Methods for Computer-Aided Circuit Analysis and Diagnosis. M. Dekker, 1998.
[5] A. Richardson, A. Lechner, T. Olbricht: “Design for Testability for Mixed Signal & Analogue Designs - From Layout to System”. Proc. Int. Conf. on Electronics, Circuits and Systems, 1998, pp. 425-432.
[6] V.C. Prasad, N.S.C. Babu: “Selection of test nodes for analog fault diagnosis in dictionary approach.” IEEE Trans. Instrum. Meas., vol. 49, no. 6, 2000, pp. 1289-1297.
[7] J.A. Starzyk, D. Liu, Zhi-H. Liu, D.E. Nelson, J. Rutkowski: “Entropy-Based Optimum Test Points Selection for Analog Fault Dictionary Techniques.” IEEE Trans. on Instrumentation and Measurement, vol. 53, no. 3, June 2004, pp. 754-761.
[8] T. Golonek, J. Rutkowski: “Genetic-Algorithm-Based Method for Optimal Analog Test Points Selection”. IEEE Trans. on Cir. and Syst.-II., vol. 54, no. 2, 2007, pp. 117-121.
[9] N. Sen, R. Saeks: “Fault Diagnosis for Linear Systems Via Multifrequency Measurements”. IEEE Trans. on Circuits and Systems, vol. 26, 1979, pp. 457-465.
[10] D. Grzechca, T. Golonek, J. Rutkowski: “Simulated Annealing with Fuzzy Fitness Function for Test Frequencies Selection”. IEEE Conference on Fuzzy Systems, FUZZ-IEEE, 2007, Imperial College London, UK.
[11] F. Grasso, A. Luchetta, S. Manetti, M.C. Piccirilla: “A Method for the Automatic Selection of Test Frequencies in Analog Fault Diagnosis”. IEEE Trans. on Instr. and Measur., vol. 56, no. 6, Dec. 2007.
[12] T. Golonek, D. Grzechca, J. Rutkowski: “Optimization of PWL Analog testing Excitation by Means of Genetic Algorithm”. Int. Conference on Signals and Electronic Systems, ICSES 2008, Kraków, Sep. 14-17, 2008, Poland, pp. 541-548.
[13] W. Hochwald, J.D. Bastian: “A DC dictionary approach for analog fault dictionary determination.” IEEE Trans. on Circuits and Systems, vol. 26, 1979, pp. 523-529.
[14] D. Grzechca, T. Golonek, J. Rutkowski: “Analog Fault AC Dictionary Creation - The Fuzzy Set Approach”. ISCAS 2006, IEEE International Symposium on Circuits and Systems, Kos, Greece, pp. 5744-5747.
[15] P. Bilski, M. Wojciechowski: “Automated Diagnostics of Analog Systems Using Fuzzy Logic Approach”. IEEE Trans. on Inst. and Measur., vol. 56, no. 6, Dec. 2007.
[16] P. Wang, S. Yang: “A New Diagnosis Approach for Handling Tolerance in Analog and Mixed-Signal Circuits by Using Fuzzy Math”. IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 53, no. 10, Oct. 2005.
[17] F. Aminian, A Modular: “Fault-Diagnostic System for Analog Electronic Circuit Using Neural Networks With Wavelet Transform as a Preprocessor”. IEEE Trans. on Inst. and Measur., vol. 56, no. 5, Oct. 2007.
[18] Z. Czaja, R. Zielonko: “On fault diagnosis of analogue electronic circuits based on transformations in multidimensional spaces”. Measurement, vol. 35, no. 3, 2004, pp. 293-301.
[19] T.R. Balen, J.V. Calvano, M.S. Lubaszewski, M.Renovell: “Functional Test of Field Programmable Analog Arrays”. Proc. of the 24th IEEE VLSI Test Symposium (VTS’06).
[20] A. Kuczyński, M. Ossowski: “Analog circuits diagnosis using discrete wavelet transform of supply current”. Metrol. Meas. Syst., vol. XVI, no. 1, 2009, pp. 77-85.
[21] M. Tadeusiewicz, S. Hałgas: “An algorithm for multiple fault diagnosis in analogue circuits.” International Journal of Circuit Theory and Applications, J.Wiley & Sons. Ltd., no. 34, 2006, pp. 607-615.
[22] P. Jantos, D. Grzechca, J. Rutkowski: “A Global Parametric Faults Diagnosis With the Use of Artificial Neural Networks.” European Conference on Circuit Theory and Design, 23-27.08.2009 Antalya, Turkey, ECCTD 2009, pp. 651-655.
[23] W. Toczek, M. Kowalewski: “Built-in test scheme for detection, classification and evaluation of nonlinearities.” Metrol. Meas. Syst., vol. XVI, no. 1, 2009, pp. 47-61.
[24] S.R. Das, J. Zakizadeh, S. Biswas, M.H. Assaf, A. R. Nayak, E. M. Petriu, W.-B. Jone, M. Sahinoglu: “Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach”. IEEE Trans. on Inst. and Measur., vol. 56, no. 3, Jun. 2007.
[25] P. Jantos, D. Grzechca, J. Rutkowski: “Global Parametric Faults identification in analog electronic circuits”. Metrol. Meas. Syst., vol. XVI, no. 3, 2009, pp. 391-402.
[26] S. Gunn: Support Vector Machines for Classification and Regression. University of Southampton, 1998.
[27] Ch. Burges: “A Tutorial on Support Vector Machines for Pattern Recognition”. Data Mining and Knowledge Discovery, Boston, 1998, pp. 121-167.
[28] H.R. Muhammad: Spice for Circuits and Electronics Using Pspice., 2nd ed., Prentice-Hall, New York, 2002.
[29] P. Mahesh: Multiclass Approaches for Support Vector Machine Based Land Cover Classification. National Institute of Technology, Haryana, India, 2008.
Kolekcja BazTech
Identyfikator YADDA bwmeta1.element.baztech-article-BSW1-0062-0005