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Fault injection stress strategies in dependability analysis

Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
The paper deals with the problem of testing computer system's susceptibility to hardware faults by means of software implemented fault injectors. Basing on our experience with fault injection techniques we present various strategies of fault stressing in relevance to fault impact analysis in the function of the application input data profile, fault injection profile in time and space, resource activities etc. We discuss the problem of test result qualification and significance. Fault hardening at the software level is also outlined. The considerations presented are illustrated with numerous experimental results obtained in Windows and Linux environments.
Rocznik
Strony
679--699
Opis fizyczny
Bibliogr. 30 poz., wykr.
Twórcy
autor
  • Institute of Computer Science, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland, jss@ii.pw.edu.pl
autor
  • Institute of Computer Science, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland
autor
  • Institute of Computer Science, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland
Bibliografia
  • Arlat, J., Crouzet, Y., Karlsson, J., Folkesson, P., Fuchs, E. and Leber, G.H.(2003) Comparison of physical and software implemented fault injection techniques. IEEE Trans. on Computers 52 (9), 1115-1135.
  • Bernrojo, L., Gonzales, I., Corno, F., Reorda, M.S., Squillero, G. and Lopez, C.(2002) An industrial environment for high level fault tolerant structures insertion and validation. Proc. 20th IEEE VLSI Test Symposium, 229-236.
  • Baldini, A., Benso, A., Chiusano, S. and Prinetto, P. (2000) ’BOND’: An interposition agents based fault injector for Windows NT. Proc. IEEED efect and Fault Tolerance in VLSI Symposium, 387-395.
  • Briand, L.C. and Pfahl, D. (2000) Using simulation for assessing the real impact of test coverage on defect coverage. IEEE Trans. on Reliability 49 (1), 60-70.
  • Carderilli. G.C., Kaddur, F., Leanori, A., Ottavi, M., Pontarelli,S. and Velzaco, R. (2002) Bit flip injection in processor based architectures: a case study. Proc. IEEE On-Line Testing Workshop, 117-128.
  • Carreira, J., Madeira, H. and Silva, J.G. (1998) Xception: a techniqueof the experimental evaluation of dependability in modern computers. IEEE Trans. on Software Engineering 24 (2), 125-136.
  • Chen, M., Tsai, T.K. and Iyer, R.K. (1997) Fault injections and tools. IEEE Computer 30 (4), 75-56.
  • Choi, G. and Iyer, R. (1992) Focus: an experimental environment for faultsensitivity analysis. IEEE Trans. on Computers 41 (12), 1515-1526.
  • Constantinescu, C. (2003) Experimental evaluation of error detection mechanisms. IEEE Trans. on Reliability 52 (1), 53-57.
  • Cukier, M., Powell, D. and Arlat, J. (1999) Coverage estimation methods for stratified fault injection. IEEE Trans. on Computers 48 (7), 707-723.
  • Derezińska, A. and Sosnowski, J. (2002) Experimental checking of fault susceptibility in a parallel algorithm. Proc. IEEE Int. Conf. on Parallel Computing in Electrical Engineering, 33-38.
  • Folkesson, P., Svensson, S. and Karlsson, J. (1998) A comparison of simulation based and scan chain implemented fault injection. Proc. IEEE Fault Tolerant Computing Symp., 284-293.
  • Gawkowski, P. and Sosnowski, J. (2001a) Experimental evaluation of fault handling mechanisms. Lecture Notes in Computer Science 2187, Springer-Verlag, 109-118.
  • Gawkowski, P. and Sosnowski, J. (2001b) Evaluation of fault effects in programmable microcontrollers. Proc. 5th IFAC Workshop PDS 01, Pergamon, 121-126.
  • Gawkowski, P. and Sosnowski, J. (2002a) Experimental validation of fault detection and fault tolerance mechanisms. Proc. IEEE Int. High Level Design Validation and Test Workshop, 181-186.
  • Gawkowski, P. and Sosnowski, J. (2002b) Using software implemented faultinserter in dependability analysis. Proc. IEEE Pacific Rim Int. Symposium on Dependable Computing, 81-88.
  • Gawkowski, P. and Sosnowski, J. (2004) Evaluation of transient fault susceptibility in microprocessor systems. Proc. of Digital System Design Euromicro Symposium, IEEE Comp. Soc., 432-439.
  • Kanawati, G., Kanawati, N. and Abraham, J. (1992) ”FERRARI”: a toolfor the validation of system dependability properties. IEEE Proc. Fault Tolerant Computing Symp., 336-344.
  • Kim, S. and Somani, A.K. (2002) Soft error sensitivity characterization for microprocessor dependability enhancement strategy. Proc. IEEE Dependable System Network Symposium, 416-428.
  • Leveugle, R. (2000) Fault injection in VHDL descriptions and emulation. Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, 414-419.
  • Madeira, H. and Silva, J.G. (1994) RIFLE: a general purpose pin-level fault injector. Lecture Notes in Computer Science 852, Springer-Verlag, 199-216.
  • Madeira, H., Some, R.R., Costa, F.D. and Rennels, D. (2002) Experimental evaluation of a COTS system for space applications. Proc. IEEE Int. Conference on Dependable Systems and Networks, 325-330.
  • Rebaudengo, M. and Reorda, M.S. (1999) Evaluating the fault tolerance capabilities of embedded systems via BDM. Proc. IEEE VLSI Test Symposium, 452-459.
  • Samson, J. (1998) A technique for automated validation of fault tolerant designs using laser fault injection. Proc. IEEE Fault Tolerant Computing Symp., 162-187.
  • Segall, Z. and Lin, T. (1988) FIAT: fault injection based automated testing environment. Proc. IEEE Fault Tolerant Computing Symp., 102-107.
  • Sieh, V., Tschade, G. and Balbach, F. (1997) Verify: evaluation of reliability using VHDL-model with embedded fault descriptions. Proc. IEEE Fault Tolerant Computing Symp., 32-36.
  • Sosnowski, J., Gawkowski, P. and Lesiak, A. (2003) Software implemented fault inserters. Proc. of IFAC PDS2003 Workshop, Pergamon, 293-298.
  • Tsai, T.K., Hsueh, M.Ch., Zhao, H., Kalbarczyk, Z. and Iyer, R.K.(1999) Stress based and path based fault injection. IEEE Trans. on Computers 48 (11), 1183-1201.
  • Vargas, F., Brum, D., Prestes, D., Bolzani, L. and Lettmin, D. (2003) On the mitigation of conducted electromagnetic immunity bymeans of SW-based fault handling mechanisms. Proc. IEEE Latin America Test Workshop, 130-135.
  • Velazco, R., Corominas, A. and Ferreyera, P. (2002) Injecting bit flip faults by means of a purely software approach. Proc. IEEE Int. Defectand Fault Tolerance in VLSI Symposium, 108-116.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BAT5-0007-0077
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