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http://yadda.icm.edu.pl:80/baztech/element/bwmeta1.element.baztech-article-BAT3-0022-0022

Czasopismo

Journal of Telecommunications and Information Technology

Tytuł artykułu

Standardization of the compact model coding: non-fully depleted SOI MOSFET example

Autorzy Grabiński, W.  Tomaszewski, D.  Lemaitre, L.  Jakubowski, A. 
Treść / Zawartość
Warianty tytułu
Języki publikacji EN
Abstrakty
EN The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.
Słowa kluczowe
EN Verilog-AMS   compact model coding   SOI MOSFET  
Wydawca Instytut Łączności - Państwowy Instytut Badawczy
Czasopismo Journal of Telecommunications and Information Technology
Rocznik 2005
Tom nr 1
Strony 135--141
Opis fizyczny Bibliogr. 8 poz., il.
Twórcy
autor Grabiński, W.
autor Tomaszewski, D.
autor Lemaitre, L.
autor Jakubowski, A.
  • Institute of Microelectronics and Optoelectronics, Warsaw University of Technology Koszykowa st 75, 00-662 Warsaw, Poland, jakubowski@imio.pw.edu.pl
Bibliografia
[1] ITRS Roadmap Update, 2003, http://www.public.itrs.net
[2] Open Verilog International, "Verilog-AMS, Language Reference Manual", Version 1.9, 1999, http://www.accellera.org/
[3] D. Tomaszewski, "Consistent DC and AC models of non-fully depleted SOI MOSFETS in strong inversion", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 111-114.
[4] L. Lemaitre, C. McAndrew, and S. Hamm, "ADMS - automatic device model synthesizer", in Proc. IEEE CICC 2002, Florida, USA, 2002, pp. 27-30.
[5] J. R. Hauser, "Small signal properties of field effect devices", IEEE Trans. Electron Dev., vol. 12, pp. 605-618, 1965.
[6] D. Tomaszewski, "A small-signal model of SOI MOSFETs capacitances". Ph.D. thesis, Institute of Electron Technology, Warsaw, 1998.
[7] L. Lemaitre, W. Grabiński, and C. McAndrew, "Compact device modeling using Verilog-A and ADMS", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 59-62.
[8] C. Lallement, F. Pecheux, and W. Grabiński, "High level description of thermodynamical effects in the EKV 2.6 most model", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 45-50.
Kolekcja BazTech
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