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http://yadda.icm.edu.pl:80/baztech/element/bwmeta1.element.baztech-article-BAT3-0022-0001

Czasopismo

Journal of Telecommunications and Information Technology

Tytuł artykułu

Challenges in scaling of CMOS devices towards 65 nm node

Autorzy Jurczak, M.  Veloso, A.  Rooyackers, R.  Augendre, E.  Mertens, S.  Rotschild, A.  Scaekers, M.  Lindsay, R.  Lauwers, A.  Henson, K.  Severi, S.  Pollentier, I.  Keersgieter de, A. 
Treść / Zawartość
Warianty tytułu
Języki publikacji EN
Abstrakty
EN The current trend in scaling transistor gate length below 60 nm is posing great challenges both related to process technology and circuit/system design. From the process technology point of view it is becoming increasingly difficult to continue scaling in traditional way due to fundamental limitations like resolution, quantum effects or random fluctuations. In turn, this has an important impact on electrical device specifications especially leakage current and the circuit power dissipation.
Słowa kluczowe
EN CMOS devices   gate dielectrics   shallow junctions   silicide   gate stack   lithography   gate patterning   silicon recess   device integration  
Wydawca Instytut Łączności - Państwowy Instytut Badawczy
Czasopismo Journal of Telecommunications and Information Technology
Rocznik 2005
Tom nr 1
Strony 3--6
Opis fizyczny Bibliogr. 9 poz., rys.
Twórcy
autor Jurczak, M.
autor Veloso, A.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Rooyackers, R.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Augendre, E.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Mertens, S.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Rotschild, A.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Scaekers, M.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Lindsay, R.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Lauwers, A.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Henson, K.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Severi, S.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Pollentier, I.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
autor Keersgieter de, A.
  • IMEC Kapeldreef st 75 3001 Leuven, Belgium
Bibliografia
[1] International Technology Roadmap for Semiconductions, 2001, http://public.itrs.net/Files/2001ITRS/Home.htm
[2] F. N. Cubaynes, J. Schmitz, C. van der Marel, H. Snijders, A. Veloso, and A. Rothschild, "Plasma nitridation optimization for sub-1 A gate dielectrics", in ECS Symp., Paris, France, 2003.
[3] A. Veloso, F. N. Cubaynes, A. Rothschild, S. Mertens, R. Degraeve, R. O'Connor, C. Olsen, L. Date, M. Schaekers, C. Dachs, and M. Jurczak, "Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm general purpose CMOS applications", in Conf. ESSDERC'03, Lisbon, Portugal, 2003.
[4] R. O'Connor, R. Degraeve, B. Kaczer, A. Veloso, G. Hughes, and G. Groeseneken, \Weilbull slope and voltage acceleration of ultra-thin (1.1{1.45 nm EOT) oxynitrides", in Conf. INFOS'03, Stara Lesna, Slovakia, 2003.
[5] L. Van den Hove, M. Goethals, K. Ronse, M. Van Bavel, and G. Vandenberghe, "Lithography for sub-90 nm applications", in IEDM Tech. Dig., San Francisco, USA, 2002, pp. 3{8.
[6] R. Lindsay, B. Pawlak, J. Kittl, K. Henson, C. Torregiani, S. Giangrandi, R. Surdeanu, W. Vandervorst, A. Mayur, J. Ross, S. McCoy, J. Gelpey, P. Stolk, and K. Maex, \A comparison of spike, ash, SPER and laser annealing for 45 nm CMOS", in MRS Symp., Paris, France, 2003.
[7] B. J. Pawlak, R. Lindsay, R. Surdeanu, X. Pages, W. Vandervorst, and K. V. D. Jeugd, "The role of F with Ge pre-amorphisation in forming PMOS junctions for the 65 nm CMOS technology node", in ECS Symp., Paris, France, 2003.
[8] R. Lindsay, B. J. Pawlak, J. Kittl, K. Henson, S. Giangrandi, R. Duffy, R. Surdeanu, W. Vandervorst, P. Stolk, and K. Maex, "Leakage optimisation of ultra-shallow junctions formed by solid phase epitaxial regrowth (SPER)", Proc. J. Vac. Sci. Technol, vol. B, Febr. 2003.
[9] A. Lauwers, J. Kittl, A. Akheyar, M. Van Dal, O. Chamirian, M. de Potter, R. Lindsay, and K. Maex, \Silicide scaling: Co, Ni or CoNi?", in ECS Symp., Paris, France, 2003.
Kolekcja BazTech
Identyfikator YADDA bwmeta1.element.baztech-article-BAT3-0022-0001
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